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參數(shù)資料
| 型號(hào)： | LTC2181IUP#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 3836K |
| 代理商： | LTC2181IUP#PBF |
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LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D1_0 to D1_15
and D2_0 to D2_15), overflow (OF2, OF1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDDandOGNDwhich
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In Double Data Rate CMOS mode, two data bits are multi-
plexed and output on each data pin. This reduces the num-
ber of digital lines by seventeen, simplifying board routing
and reducing the number of input pins needed to receive
the data. The data outputs (D1_0_1, D1_2_3, D1_4_5,
D1_6_7, D1_8_9, D1_10_11, D1_12_13, D1_14_15,
D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
D2_12_13, D2_14_15), overflow (OF2_1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDDandOGNDwhich
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs. Note that the overflow for both ADC
channels is multiplexed onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
are eight LVDS output pairs per ADC channel (D1_0_1+/
D1_0_1– through D1_14_15+/D1_14_15– and D2_0_1+/
D2_0_1– through D2_14_15+/D2_14_15–) for the digital
output data. Overflow (OF2_1+/OF2_1–) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that the overflow for both ADC channels
is multiplexed onto the OF2_1+/OF2_1– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100 differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100 termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100 termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the
analog input is either over-ranged or under-ranged. The
overflow bit has the same pipeline latency as the data bits.
In Full-Rate CMOS mode each ADC channel has its own
overflow pin (OF1 for channel 1, OF2 for channel 2). In
DDR CMOS or DDR LVDS mode the overflow for both ADC
channels is multiplexed onto the OF2_1 output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2181IUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2180IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2180IUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2180CUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2182CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2182 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs |
| LTC2182CUP#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN |
| LTC2182CUP#TRPBF | 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 65MSPS 64-QFN |
| LTC2182IUP#PBF | 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN |
| LTC2182IUP#PBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP |
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