參數(shù)資料
型號： LTC2180IUP#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁數(shù)： 19/36頁
文件大?。?/td> 3836K
代理商： LTC2180IUP#PBF
LTC2182/LTC2181/LTC2180
26
218210f
allowed so the on-chip references can settle from the
slight temperature shift caused by the change in supply
current as the A/D leaves nap mode. Either channel 2 or
both channels can be placed in nap mode; it is not possible
to have channel 1 in nap mode and channel 2 operating
normally.
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
DEVICE PROGRAMMING MODES
The operating modes of the LTC2182/LTC2181/LTC2180
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flex-
ibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V, or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI/SDO Power Down Control Bit
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
APPLICATIONS INFORMATION
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D15-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: Outputs change from
10101010101010101 to 01010101010101010 on
alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the Test Patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehigh-impedancedisabled
state is intended for in-circuit testing or long periods of
inactivity – it is too slow to multiplex a data bus between
multiple converters at full speed. When the outputs are
disabled both channels should be put into either sleep or
nap mode.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of
time required to recover from sleep mode depends on the
size of the bypass capacitors on VREF, REFH, and REFL.
For the suggested values in Fig. 8, the A/D will stabilize
after 2ms.
InnapmodetheA/Dcoreispowereddownwhiletheinternal
reference circuits stay active, allowing faster wakeup than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50s should be
相關(guān)PDF資料
PDF描述
LTC2180IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180CUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2182CUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2182IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181CUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2181 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs
LTC2181CUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 40Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN
LTC2181CUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 40Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2181CUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 40Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 40MSPS 64-QFN
LTC2181CUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 40Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*