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參數(shù)資料
| 型號： | LTC2180CUP#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 3836K |
| 代理商： | LTC2180CUP#PBF |
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LTC2182/LTC2181/LTC2180
28
218210f
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is
Automatically Set Back to Zero at the End of the SPI Write Command. The Reset Register Is Write-Only. Data Read Back from the
Reset Registar Will Be Random.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
Power Down Control Bits
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period 3/8)
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
相關PDF資料 |
PDF描述 |
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| LTC2182CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2182IUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2181CUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2181CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2180CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2180IUP#PBF | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN |
| LTC2180IUP#PBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP |
| LTC2180IUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 25MSPS 64-QFN |
| LTC2180IUP#TRPBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R |
| LTC2181 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs |
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