參數(shù)資料
型號(hào)： LTC2175IUKG-14#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/34頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 125MSPS QUAD 52QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 646mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-QFN（7x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2175-14/
LTC2174-14/LTC2173-14
26
21754314fa
applicaTions inForMaTion
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in SLEEP Mode.
This Bit is Automatically Set Back to Zero at the End of the SPI Write Command.
The Reset Register is Write Only.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_4
NAP_3
NAP_2
NAP_1
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
then SDO can be left floating and no pull-up resistor is
needed.Table4showsamapofthemodecontrolregisters.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
GROUNDING AND BYPASSING
The LTC2175-14/LTC2174-14/LTC2173-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, OVDD, VCM, VREF, REFH and REFL pins. By-
pass capacitors must be located as close to the pins as
possible. Of particular importance is the 0.1F capacitor
between REFH and REFL. This capacitor should be on the
same side of the circuit board as the A/D, and as close to
the device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2F capacitor
between REFH and REFL can be somewhat further away.
Thetracesconnectingthepinsandbypasscapacitorsmust
be kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
MostoftheheatgeneratedbytheLTC2175-14/LTC2174-14/
LTC2173-14istransferredfromthediethroughthebottom-
sideExposedPadandpackageleadsontotheprintedcircuit
board. For good electrical and thermal performance, the
Exposed Pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
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