參數(shù)資料
型號(hào)： LTC2173CUKG-14#TRPBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 18/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS QUAD 52QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 454mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 52-QFN（7x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
25
21754314fa
LTC2175-14/
LTC2174-14/LTC2173-14
applicaTions inForMaTion
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50s should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2175-14/LTC2174-14/
LTC2173-14 can be programmed by either a parallel in-
terface or a simple serial interface. The serial interface has
more flexibility and can program all available modes. The
parallel interface is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V, or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serialinterfacethatprogramtheA/Dmodecontrolregisters.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams sections). During a read back command the
register is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200 impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
Pin
DESCRIPTION
CS
2-Lane / 1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
SCK
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
SDO
Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
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