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參數(shù)資料
| 型號： | LTC2165IUK#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 663K |
| 代理商： | LTC2165IUK#TRPBF |
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LTC2165/LTC2164/LTC2163
22
216543f
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
applicaTions inForMaTion
Figure 12. Sinusoidal Encode Drive
Figure 13. PECL or LVDS Encode Drive
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to3.3VCMOSlogiclevelscanbeused.TheENC+threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
50
100
0.1F
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2165
2165 F12
ENC–
ENC+
T1
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
2165 F13
LTC2165
Figure 10. Equivalent Encode Input
Circuit for Differential Encode Mode
VDD
LTC2165
2165 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
ENC+
ENC–
2165 F11
0V
1.8V TO 3.3V
LTC2165
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input
Circuit for Single-Ended Encode Mode.
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12, 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be
taken above VDD (up to 3.6V), and the common mode
range is from 1.1V to 1.6V. In the differential encode
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single-ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
The single ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
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| LTC2165CUK#TRPBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2163IUK#PBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2170CUKG-12#TRPBF | 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LTC2170-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs |
| LTC2170-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Quad 14-Bit, 125Msps ADC with Integrated Drivers |
| LTC2170CUKG-12#PBF | 功能描述:IC ADC 12BIT SER/PAR 25M 52-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2170CUKG-12#TRPBF | 功能描述:IC ADC 12BIT SER/PAR 25M 52-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2170CUKG-12PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs |
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