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參數資料
| 型號： | LTC2163CUK#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48 |
| 文件頁數： | 16/36頁 |
| 文件大?。?/td> | 663K |
| 代理商： | LTC2163CUK#PBF |
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LTC2165/LTC2164/LTC2163
23
216543f
applicaTions inForMaTion
to make the sampling clock have a 50%(±5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
TheLTC2165/LTC2164/LTC2163canoperateinthreedigital
output modes: full rate CMOS, double data rate CMOS (to
halvethenumberofoutputlines),ordoubledatarateLVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D0 to D15),
overflow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of digital lines by eight, simplifying board routing
and reducing the number of input pins needed to receive
thedata.Thedataoutputs(D0_1,D2_3,D4_5,D6_7,D8_9,
D10_11, D12_13, D14_15), overflow (OF), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDDandOGNDwhich
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
When using double data rate CMOS at sample rates above
100Msps, the SNR may degrade slightly, about 0.2dB to
0.5dB depending on load capacitance and board layout.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexedandoutputoneachdifferentialoutputpair.Thereare
eight LVDS output pairs (D0_1+/D0_1– through D14_15+/
D14_15–) for the digital output data. Overflow (OF+/OF–)
and the data output clock (CLKOUT+/CLKOUT–) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100 differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100 termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100 termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the
analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
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相關代理商/技術參數 |
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| LTC2163IUK#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 80MSP 48QFN |
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| LTC2164CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single 105Msps 16-bit Parallel/Serial (SPI)/LVDS 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 105M 48QFN 制造商:Linear Technology 功能描述:ADC 16BIT 105MSPS 48QFN 制造商:Linear Technology 功能描述:ADC, 16BIT, 105MSPS, 48QFN |
| LTC2164CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single 105Msps 16-bit Parallel/Serial (SPI)/LVDS 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 105M 48QFN |
| LTC2164IUK#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 105M 48QFN |
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