參數(shù)資料
型號: LTC2160IUK#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48
文件頁數(shù): 18/36頁
文件大?。?/td> 651K
代理商: LTC2160IUK#TRPBF
LTC2162/LTC2161/LTC2160
25
216210f
applicaTions inForMaTion
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital Output Signal
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode is
enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13,
D15) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12, D14), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
thatiscenteredaroundmid-scale,thedigitaloutputstoggle
between mostly 1’s and mostly 0’s. This simultaneous
switchingofmostofthebitswillcauselargecurrentsinthe
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13, D15.) The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function can
be on at the same time. The alternate bit polarity mode is
enabledbyseriallyprogrammingmodecontrolregisterA4.
CLKOUT
OF
D15/D0
D14/D0
D2/D0
D1/D0
D0
216210 F15
OF
D15
D14
D2
D1
D0
RANDOMIZER
ON
D15
FPGA
PC BOARD
D14
D2
D1
D0
216210 F16
D0
D1/D0
D2/D0
D14/D0
D15/D0
OF
CLKOUT
LTC2162
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PDF描述
LTC2162CUK#TRPBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2162IUK#PBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2162IUK#TRPBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2161CUK#TRPBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
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