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參數(shù)資料
| 型號： | LTC2156IUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 647K |
| 代理商： | LTC2156IUP-14#PBF |
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21576514f
LTC2157-14/
LTC2156-14/LTC2155-14
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is neces-
sary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
GROUNDING AND BYPASSING
The LTC215X-14 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF pins. Bypass capacitors must be
located as close to the pins as possible. Size 0402 ceramic
capacitors are recommended. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC215X-14 is trans-
ferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
APPLICATIONS INFORMATION
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