參數資料
型號: LTC2151IUJ-14#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁數: 19/32頁
文件大小: 790K
代理商: LTC2151IUJ-14#TRPBF
LTC2152-14/
LTC2151-14/LTC2150-14
26
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applicaTions inForMaTion
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” indicates an unused bit.
REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All mode control registers are reset to 00h. After the Reset SPI Write Command is Complete, Bit D7 is
Automatically Set Back to Zero. The Reset Register is Write Only.
Bits 6-0
Unused bit.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
SLEEP
NAP
0
Bits 7-4
Unused, these bits are read back as 0.
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode
Bit 1-0
Must be set to 0.
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, these bits are read back as 0.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUTdelayed by 45° (Clock Period 1/8)
10 = CLKOUT+/CLKOUTdelayed by 90° (Clock Period 1/4)
11 = CLKOUT+/CLKOUTdelayed by 135° (Clock Period 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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