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15
21521014f
LTC2152-14/
LTC2151-14/LTC2150-14
pin FuncTions
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to
ground with 0.1F ceramic capacitor. Pins 1, 2 can share
a bypass capacitor.
GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC
Power Ground. The exposed pad must be soldered to the
PCB ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 × VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2F ceramic capacitor. Nominally 1.25V.
VCM (Pin 9): Common Mode Bias Output; nominally equal
to 0.439 VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1F
ceramic capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass
to ground with a 0.1F ceramic capacitor.
OGND (Pin 21): LVDS Driver Ground.
SDO (Pin 36): Serial Interface Data Output. In serial pro-
grammingmode,(PAR/SER=0V),SDOistheoptionalserial
interface data output. Data on SDO is read back from the
mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2k pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
SDI(Pin37):SerialInterfaceDataInput.Inserialprogram-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registersontherisingedgeofSCK.Inparallelprogramming
mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA
LVDS output current (see Table 2).
SCK (Pin 38): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interfaceclockinput.Inparallelprogrammingmode(PAR/
SER = VDD), SCK controls the sleep mode (see Table 2).
CS (Pin 39): Serial Interface Chip Select Input. In serial
programming mode, (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers. In
parallelprogrammingmode(PAR/SER=VDD),CScontrols
the clock duty cycle stabilizer (see Table 2).
PAR/SER (Pin 40): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that control the A/D operating modes. Connect to VDD to
enabletheparallelprogrammingmodewhereCS,SCKand
SDI become parallel logic inputs that control a reduced
set of the A/D operating modes. PAR/SER should be con-
nected directly to ground or the VDD of the part and not
be driven by a logic signal.