參數(shù)資料
型號(hào)： LTC2150CUP-14#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封裝： 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 4005K
代理商： LTC2150CUP-14#PBF
LTC2152-14/
LTC2151-14/LTC2150-14
24
21521014p
Alternate Bit Polarity
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes (activate by setting
DTESTON) that force the A/D data outputs (OF, D13 to
D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs, includ-
ing OF and CLKOUT, are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Power-Down Modes
The A/D may be placed in a power-down mode to conserve
power. In sleep mode, the entire A/D converter is powered
down, resulting in < 2mW power consumption. If the en-
code input signal is not disabled, the power consumption
will be higher (up to 2mW at 250Msps). Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SCK (parallel programming mode).
In serial programming mode it is also possible to disable
channel B while leaving channel A in normal operation.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF .
For the suggested values in Figure 1, the A/D will stabi-
lize after 0.1ms + 2500 tp where tp is the period of the
sampling clock.
Nap Mode
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wakeup. Recovering from nap mode requires at least 100
clock cycles. Wake-up time from nap mode is guaranteed
only if the clock is kept running, otherwise power-down,
wake-up time conditions apply. Nap mode is enabled by
power-down register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC215X-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
APPLICATIONS INFORMATION
相關(guān)PDF資料
PDF描述
LTC2151CUP-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2157CUP-14#PBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2157CUP-14#TRPBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2157IUP-14#PBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
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