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參數(shù)資料
| 型號： | LTC2150CUJ-14#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 790K |
| 代理商： | LTC2150CUJ-14#TRPBF |
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21
21521014f
LTC2152-14/
LTC2151-14/LTC2150-14
applicaTions inForMaTion
the encode inputs directly. Otherwise, a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
via SPI Register A2 (see SPI Control Register) or by CS
in parallel programming mode.
Figure 9. Sinusoidal Encode Drive
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double-data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are seven LVDS output pairs (D0_1+/
D0_1– through D12_13–/D12_13+). Overflow (OF+/OF–)
and the data output clock (CLKOUT+/CLKOUT–) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage.
LTC2152-14
T1
VDD
21521014 F09
1.2V
10k
50
100
50
0.1F
T1: MACOM ETC1-1-13
Figure 10. PECL or LVDS Encode Drive
VDD
LTC2152-14
PECL OR
LVDS INPUT
21521014 F10
1.2V
10k
100
0.1F
ENC+
ENC–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2152CUJ-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2152IUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2150IUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2152CUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2151CUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2150CUP-14PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit 250Msps/ 210Msps/170Msps ADCs |
| LTC2150IUJ-12#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 12BIT 170MSPS 40QFN |
| LTC2150IUJ-12#TRPBF | 制造商:Linear Technology 功能描述:Single ADC Pipelined 170Msps 12-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 12BIT 170MSPS 40QFN |
| LTC2150IUJ-14#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 14-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 14BIT SPI 170MSPS 40QFN |
| LTC2150IUJ-14#TRPBF | 制造商:Linear Technology 功能描述:Single ADC Pipelined 170Msps 14-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 14BIT SPI 170MSPS 40QFN |
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