- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄39410 > LTC2140IUP-14#PBF (LINEAR TECHNOLOGY CORP) 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 PDF資料下載
參數(shù)資料
| 型號： | LTC2140IUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 528K |
| 代理商： | LTC2140IUP-14#PBF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
LTC2142-14/
LTC2141-14/LTC2140-14
22
21421014f
50Ω
100Ω
0.1μF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2142
21421014 F12
ENC–
ENC+
0.1μF
T1
Figure 12. Sinusoidal Encode Drive
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1μF
21421014 F13
LTC2142
Figure 13. PECL or LVDS Encode Drive
VDD
LTC2142
21421014 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
30k
ENC+
ENC–
21421014 F11
0V
1.8V TO 3.3V
LTC2142
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single ended encode mode. For good
jitter performance ENC+ and ENC– should have fast rise
and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance, ENC+ should have
fast rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2142-14/LTC2141-14/LTC2140-14 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.) The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode). Note that double data rate CMOS cannot be selected
in the parallel programming mode.
APPLICATIONS INFORMATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2140CUP-14#TRPBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2141IUP-14#TRPBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2141CUP-14#TRPBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2143CUP-14#TRPBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2143IUP-14#PBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2141-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs |
| LTC2141CUP-12#PBF | 功能描述:IC ADC DUAL 12BIT 40MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2141CUP-12#TRPBF | 功能描述:IC ADC DUAL 12BIT 40MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2141CUP-14#PBF | 功能描述:IC ADC DUAL 14BIT 40 MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2141CUP-14#TRPBF | 功能描述:IC ADC DUAL 14BIT 40 MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。