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參數(shù)資料
| 型號： | LTC2053HMS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 0K |
| 描述： | IC AMP INST 0-DRFT R-R I/O 8MSOP |
| 標準包裝： | 50 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 0.2 V/µs |
| 增益帶寬積： | 200kHz |
| 電流 - 輸入偏壓： | 4nA |
| 電壓 - 輸入偏移： | 5µV |
| 電流 - 電源： | 950µA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 11 V，±1.35 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 管件 |
LTC2053/LTC2053-SYNC
2053syncfc
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results
in an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin
to the voltage on the –IN pin every cycle. The resulting
input charging current decays exponentially during each
input sampling period with a time constant equal to RSCS.
If the voltage disturbance due to these currents settles
before the end of the sampling period, there will be no
errors due to source resistance or the source resistance
mismatch between –IN and +IN. With RS less than 10k,
no DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there
are no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents previously described
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
TheLTC2053usesasampleddatatechniqueand,therefore,
contains some clocked digital circuitry. It is, therefore,
sensitive to supply bypassing. For single or dual supply
operation, a 0.1F ceramic capacitor must be connected
between Pin 8 (V+) and Pin 4 (V–) with leads as short as
possible.
Synchronizing to an External Clock
(LTC2053-SYNC Only)
TheLTC2053hasaninternallygeneratedsampleclockthat
is typically 3kHz. There is no need to provide the LTC2053
with a clock. However, in some applications, it may be
desirable for the user to control the sampling frequency
more precisely to avoid undesirable aliasing. This can be
done with the LTC2053-SYNC. This device uses Pin 1 as a
clock input whereas the LTC2053 uses Pin 1 as an enable
pin. If CLK (Pin 1) is left floating on the LTC2053-SYNC,
the device will run on its internal oscillator, similar to the
LTC2053. However, if not externally synchronizing to a
system clock, it is recommended that the LTC2053 be
used instead of the LTC2053-SYNC because the LTC2053-
SYNC is sensitive to parasitic capacitance on the CLK pin
when left floating. Clocking the LTC2053-SYNC is accom-
plished by driving the CLK pin at 8 times the desired
sample clock frequency. This completely disables the
internal clock. For example, to achieve the nominal
LTC2053sampleclockrateof3kHz,a24kHzexternalclock
should be applied to the CLK pin of the LTC2053-SYNC.
applicaTions inForMaTion
–
+
–
+
VIN
V+IN
VOUT
V–IN
3
8
5V
4
5
6
7
2
–
+
–
+
VIN
V+IN
VOUT
V–IN
VREF
–5V
3
8
5V
–5V < V–IN < 5V AND V–IN – VREF < 5.5V
–5V < V+IN < 5V AND V+IN – VREF < 5.5V
–5V < VIN + VREF < 3.7V
SINGLE SUPPLY, UNITY GAIN
–
+
–
+
VIN
V+IN
VOUT
V–IN
3
8
5V
4
5
6
7
2
0V < V+IN < 5V
0V < V–IN < 5V
0V < VIN < 3.7V
VOUT = VIN
SINGLE SUPPLY, UNITY GAIN
DUAL SUPPLY, NONUNITY GAIN
4
5
6 R2
R1
7
2
VOUT = 1 +
VIN + VREF
R2
R1
0V < V–IN < 5V AND V–IN – VREF < 5.5V
0V < V+IN < 5V AND V+IN – VREF < 5.5V
0V < VIN + VREF < 3.7V
VOUT = VIN + VREF
–
+
–
+
VIN
V+IN
VOUT
V–IN
–5V
3
2053 F01
8
–5V < V–IN < 5V AND V–IN – VREF < 5.5V
–5V < V+IN < 5V AND V+IN – VREF < 5.5V
–5V < VIN + VREF < 3.7V
DUAL SUPPLY, NONUNITY GAIN
4
5
6 R2
R1
7
2
VOUT = 1 +
(VIN + VREF)
R2
R1
Figure 1
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