參數(shù)資料
型號(hào): LTC2050HVIS5
元件分類: 運(yùn)算放大器
英文描述: Chopper-Stabilized Operational Amplifier
中文描述: 斬波穩(wěn)定運(yùn)算放大器
文件頁數(shù): 10/12頁
文件大?。?/td> 169K
代理商: LTC2050HVIS5
7
LTC2050/LTC2050HV
the op amp. This form of clock feedthrough is independent
of the magnitude of the input source resistance or the
magnitude of the gain setting resistors. The LTC2050 has
a residue clock feedthrough of less then 1
VRMS input
referred at 7.5kHz.
The second form of clock feedthrough is caused by the
small amount of charge injection occurring during the
sampling and holding of the op amp’s input offset voltage.
The current spikes are multiplied by the impedance seen
at the input terminals of the op amp, appearing at the
output multiplied by the closed loop gain of the op amp. To
reduce this form of clock feedthrough, use smaller valued
gain setting resistors and minimize the source resistance
at the input. If the resistance seen at the inputs is less than
10k, this form of clock feedthrough is less than 1
VRMS
input referred at 7.5kHz, or less than the amount of residue
clock feedthrough from the first form described above.
Placing a capacitor across the feedback resistor reduces
either form of clock feedthrough by limiting the bandwidth
of the closed loop gain.
APPLICATIONS INFORMATION
WU
U
Shutdown
The LTC2050 includes a shutdown pin in the 6-lead
SOT-23 and the SO-8 version. When this active low pin is
high or allowed to float, the device operates normally.
When the shutdown pin is pulled low, the device enters
shutdown mode; supply current drops to 3
A, all clocking
stops, and both inputs and output assume a high imped-
ance state.
Clock Feedthrough, Input Bias Current
The LTC2050 uses auto-zeroing circuitry to achieve an
almost zero DC offset over temperature, common mode
voltage, and power supply voltage. The frequency of the
clock used for auto-zeroing is typically 7.5kHz. The term
clock feedthrough is broadly used to indicate visibility of
this clock frequency in the op amp output spectrum. There
are typically two types of clock feedthrough in auto zeroed
op amps like the LTC2050.
The first form of clock feedthrough is caused by the
settling of the internal sampling capacitor and is input
referred; that is, it is multiplied by the closed loop gain of
TEST CIRCUITS
+
LTC2050
V+
V
10
1
2
3
4
5
RL
2050 TC01
100k
OUTPUT
+
LTC2050
+
LT1012
10
1
3
4
2050 TC02
100k
475k
316k
158k
0.1
F
0.01
F
0.01
F
TO X-Y
RECORDER
FOR 1Hz NOISE BW INCREASE ALL THE CAPACITORS BY A FACTOR OF 10.
Electrical Characteristics
Test Circuit
DC-10Hz Noise Test Circuit
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