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參數(shù)資料
| 型號(hào)： | LTC1871HMS#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 0.05 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁(yè)數(shù)： | 2/36頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | LTC1871HMS#TR |
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LTC1871
10
1871fe
MOSFET RDS(ON). If the ITH pin drops below 0.30V, the
Burst Mode comparator B1 will turn off the power MOSFET
and scale back the quiescent current of the IC to 250μA
(sleep mode). In this condition, the load current will be
supplied by the output capacitor until the ITH voltage rises
above the 50mV hysteresis of the burst comparator. At
light loads, short bursts of switching (where the average
inductor current is 20% of its maximum value) followed
by long periods of sleep will be observed, thereby greatly
improving converter efciency. Oscilloscope waveforms
illustrating Burst Mode operation are shown in Figure 3.
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 2V,
Burst Mode operation is disabled. The internal, 0.525V
buffered ITH burst clamp is removed, allowing the ITH
pin to directly control the current comparator from no
load to full load. With no load, the ITH pin is driven below
0.30V, the power MOSFET is turned off and sleep mode
is invoked. Oscilloscope waveforms illustrating this mode
of operation are shown in Figure 4.
When an external clock signal drives the MODE/SYNC
pin at a rate faster than the chip’s internal oscillator, the
oscillator will synchronize to it. In this synchronized mode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the ex-
pense of overall system efciency of light loads.
When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the in-
ternal oscillator ramp is terminated early and the slope
compensation is increased by approximately 30%. As
a result, in applications requiring synchronization, it is
recommended that the nominal operating frequency of
the IC be programmed to be about 75% of the external
clock frequency. Attempting to synchronize to too high an
external frequency (above 1.3fO) can result in inadequate
slope compensation and possible subharmonic oscillation
(or jitter).
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
Figure 3. LTC1871 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
Figure 4. LTC1871 Low Output Current Operation with
Burst Mode Operation Disabled (MODE/SYNC = INTVCC)
VOUT
50mV/DIV
IL
5A/DIV
10μs/DIV
1871 F03
VIN = 3.3V
VOUT = 5V
IOUT = 500mA
MODE/SYNC = 0V
(Burst Mode OPERATION)
VOUT
50mV/DIV
IL
5A/DIV
2μs/DIV
1871 F04
VIN = 3.3V
VOUT = 5V
IOUT = 500mA
MODE/SYNC = INTVCC
(PULSE-SKIP MODE)
OPERATION
Figure 5. MODE/SYNC Clock Input and Switching
Waveforms for Synchronized Operation
1871 F05
2V TO 7V
MODE/
SYNC
GATE
IL
tMIN = 25ns
0.8T
D = 40%
T
T = 1/fO
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