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參數(shù)資料
| 型號： | LTC1856CG#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 8-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | 5.3 MM, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 300K |
| 代理商： | LTC1856CG#TR |
19
LTC1854/LTC1855/LTC1856
185456fa
APPLICATIO S I FOR ATIO
WU
UU
MUX ADDRESS
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM. Both the “+” and “–” inputs are sampled simulta-
neously so common mode noise is rejected. Bits 5 and 6
of the input words are Don’t Care bits.
POWER DOWN SELECTION (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) deter-
mine the power shutdown mode of the LTC1854/LTC1855/
LTC1856. See Table 2. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the con-
version which is indicated by the rising edge of the BUSY
signal. Nap mode lasts until the falling edge of the 2nd SCK
(see Figure 9). Automatic nap will be achieved if Nap = 1
is selected each time an input word is written to the ADC.
Table 2. Power Down Selection
NAP
SLEEP
POWER DOWN MODE
0
Power On
1
0
Nap
X
1
Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previous
conversion result can be clocked out and the Sleep mode
will start on the falling edge of the last (16th) SCK. Notice
that the CONVST should stay either high or low in sleep
mode (see Figure 10). To wake up from the sleep mode,
apply a rising edge on the CONVST signal and then apply
Sleep = 0 on the next SDI word and the part will wake up
on the falling edge of the last (16th) SCK (see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10
mA)
remain. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 16).
The wake-up time is typically 40ms with the recom-
mended 10
mF capacitor connected on the REFCOMP pin.
DYNAMIC PERFORMANCE
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical LTC1856 FFT plot which yields a SINAD of 87dB
and THD of – 101dB.
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