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參數(shù)資料
| 型號： | LTC1856CG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 100KSPS 28-SSOP |
| 標準包裝： | 47 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，雙極；4 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1347 (CN2011-ZH PDF) |
5
LTC1854/LTC1855/LTC1856
185456fa
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25
∞C. (Note 5)
TI I G CHARACTERISTICS
U
W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX) Maximum Sampling Frequency
Through CH0 to CH7 Inputs
●
100
kHz
+, ADC– Only
166
kHz
tCONV
Conversion Time
●
45
ms
tACQ
Acquisition Time
Through CH0 to CH7 Inputs
●
4
ms
Through ADC+, ADC– Only
1
ms
fSCK
SCK Frequency
(Note 13)
●
0
20
MHz
tr
SDO Rise Time
See Test Circuits
6
ns
tf
SDO Fall Time
See Test Circuits
6
ns
t1
CONVST High Time
●
40
ns
t2
CONVST to BUSY Delay
CL = 25pF, See Test Circuits
●
15
30
ns
t3
SCK Period
●
50
ns
t4
SCK High
●
10
ns
t5
SCK Low
●
10
ns
t6
Delay Time, SCK
to SDO Valid
CL = 25pF, See Test Circuits
●
25
45
ns
t7
Time from Previous SDO Data Remains
CL = 25pF, See Test Circuits
●
520
ns
Valid After SCK
t8
SDO Valid After RD
CL = 25pF, See Test Circuits
●
11
30
ns
t9
RD
to SCK Setup Time
●
20
ns
t10
SDI Setup Time Before SCK
≠
●
0ns
t11
SDI Hold Time After SCK
≠
●
7ns
t12
SDO Valid Before BUSY
≠
RD = Low, CL = 25pF, See Test Circuits
●
520
ns
t13
Bus Relinquish Time
See Test Circuits
●
10
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1854.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error.
Note 12: Recovers to specified performance after (2 FS) input
overvoltage.
Note 13: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
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| LTC1857CG#PBF | 制造商:Linear Technology 功能描述:ADC, 8CH, 12BIT, 100KSPS, SSOP-28 |
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