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參數(shù)資料
| 型號： | LTC1851CFW |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS 48-TSSOP |
| 標準包裝： | 39 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1347 (CN2011-ZH PDF) |
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13
LTC1850/LTC1851
18501f
APPLICATIO S I FOR ATIO
WU
UU
The LTC1850/LTC1851 are complete and very flexible data
acquisition systems. They consist of a 10-bit/12-bit,
1.25Msps capacitive successive approximation A/D con-
verter with a wideband sample-and-hold, a configurable
8-channel analog input multiplexer, an internal reference
and reference buffer amplifier, a 16-bit parallel digital
output and digital control logic including a programmable
sequencer.
CONVERSION DETAILS
The core analog-to-digital converter in the LTC1850/
LTC1851 uses a successive approximation algorithm and
an internal sample-and-hold circuit to convert an analog
signal to a 10-bit/12-bit parallel output. Conversion start
is controlled by the CS and CONVST inputs. At the start of
the conversion, the successive approximation register
(SAR) is reset. Once a conversion cycle is begun, it cannot
be restarted. During the conversion, the internal differen-
tial 10-bit/12-bit capacitive DAC output is sequenced by
the SAR from the most significant bit (MSB) to the least
significant bit (LSB). The outputs of the analog input
multiplexer are connected to the sample-and-hold ca-
pacitors (CSAMPLE) during the acquire phase and the
comparator offset is nulled by the zeroing switches. In
this acquire phase, a minimum delay of 150ns will provide
enough time for the sample-and-hold capacitors to ac-
quire the analog signal. During the convert phase, the
comparator zeroing switches are open, putting the com-
parator into compare mode. The input switches connect
CSAMPLE to ground, transferring the differential analog
input charge onto the summing junction. This input
charge is successively compared with the binary weighted
charges supplied by the differential capacitive DAC. Bit
decisions are made by the high speed comparator. At the
end of the conversion, the differential DAC output bal-
ances the input charges. The SAR contents (a 10-bit/
12-bit data word), which represents the difference of the
analog input multiplexer outputs, and the 4-bit address
word are loaded into the 14-bit/16-bit output latches.
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency. The effective number of bits (ENOBs) is a
measurement of the resolution of an ADC and is directly
related to the S/(N + D) by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where ENOB is the effective number of bits and S/(N + D)
is expressed in dB. At the maximum sampling rate of
1.25MHz, the LTC1850/LTC1851 maintain near ideal
ENOBs up to and beyond the Nyquist input frequency of
625kHz.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD
Log
VVV
Vn
V
=
++
+
20
23
4
1
22
2
...
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The LTC1850/LTC1851
have good distortion performance up to the Nyquist fre-
quency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LTC1851CFW#PBF | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC1851CFW#TR | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| LTC1851CFW#TRPBF | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| LTC1851CFWPBF | 制造商:Linear Technology 功能描述:ADC,LTC1851 12bit 1.25MSPS 8 ch TSSOP |
| LTC1851IFW | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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