參數(shù)資料
型號(hào): LTC1840
廠商: Linear Technology Corporation
元件分類: DC/DC變換器
英文描述: RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述: 雙風(fēng)扇控制器,帶有2線接口
文件頁數(shù): 8/12頁
文件大小: 203K
代理商: LTC1840
LTC1840
OPERATIOU
8
1840f
LTC1840 Device Addressing
It is possible to configure the part to operate with any one
of nine separate addresses through the three state A0 and
A1 pins. Table 1 shows the correspondence of addresses
to the states of the pins:
Table 1. Device Addressing
LTC1840
Device Address
A0
L
NC
NC
H
L
H
NC
H
L
2-Wire Bus Slave Address Bits
(B7,B6,B5 = 111)
B3
0
0
0
0
1
1
1
1
0
A1
NC
H
NC
NC
L
H
L
L
H
B4
0
0
0
0
0
0
0
0
1
B2
0
0
1
1
0
0
1
1
0
B1
0
1
0
1
0
1
0
1
0
For the A0 and A1 lines, L refers to a grounded pin, H is a
pin shorted to V
CC
and NC is no connect. The pin voltage
will be set to approximately V
CC
/2 when not connected.
Bits B7, B6 and B5 of the address are hardwired to 111.
Register Addresses and Contents
Fault conditions are cleared by the action of writing to the
fault register, but the data byte from the write command is
not actually loaded into the register.
A TACHA/B FLT (fault) bit will be high if the corresponding
TACHA/B FLTEN bit in the status register has been set high
and the corresponding TACHA/B counter has overflowed
its maximum count of 255. These faults are latched
internally and must be cleared by writing to the fault
register or by setting TACHA/B FLTEN low. The fault will be
reasserted if the counter is still in overflow after a write to
the fault register. The TACH FLT bits power-up in the low
state.
The blast and timer bits become high after blasting and
serial access time-out events, respectively.
A high GPIOX FLT bit reflects that the GPIOX pin has
caused a fault condition; to do so, the pin must be enabled
as fault producing in the GPIO setup register (GPIOX
FLTEN set high) and the logic state of the pin must change
after the enable. The fault is latched internally and must be
cleared through software by writing to the fault register or
by setting GPIOX FLTEN low; a change in the state of the
GPIOX pin from its state at the point of the fault register
being written will cause another fault to be signalled.
Register
Name
(R/W)
FAULT
Register
Address
R2 R1 R0
000
Data Byte
D7
D6
D5
Blast
(0)
DIV1
(0)
Bit 5
(0)
Bit 5
(0)
Cnt A5
(1)
Cnt B5
(1)
GPIO2 Pin
(N/A)
GPIO2 BLNK
(0)
D4
D3
D2
D1
D0
TACHA FLT
(0)
TACHA FLTEN TACHB FLTEN
(0)
MSB
(0)
MSB
(0)
Cnt A7
(1)
Cnt B7
(1)
GPIO4 Pin
(N/A)
GPIO4 BLNK
(0)
TACHB FLT
(0)
Timer
(0)
DIV0
(0)
Bit 4
(0)
Bit 4
(0)
Cnt A4
(1)
Cnt B4
(1)
GPIO1 Pin
(N/A)
GPIO1 BLNK
(0)
GPI04 FLT
(0)
*See Note 2
(0/1)
Bit 3
(0)
Bit 3
(0)
Cnt A3
(1)
Cnt B3
(1)
GPIO4 Reg
(1)
GPIO4 FLTEN
(0)
GPI03 FLT
(0)
GPI02 FLT
(0)
GPI01 FLT
(0)
STATUS
001
(0)
Bit 6
(0)
Bit 6
(0)
Cnt A6
(1)
Cnt B6
(1)
GPIO3 Pin
(N/A)
GPIO3 BLNK
(0)
(0)
Bit 2
(0)
Bit 2
(0)
Cnt A2
(1)
Cnt B2
(1)
GPIO3 Reg
(1)
GPIO3 FLTEN
(0)
(0)
Bit 1
(0)
Bit 1
(0)
Cnt A1
(1)
Cnt B1
(1)
GPIO2 Reg
(1)
GPIO2 FLTEN
(0)
(1)
LSB
(0)
LSB
(0)
Cnt A0
(1)
Cnt B0
(1)
GPIO1 Reg
(1)
GPIO1 FLTEN
(0)
DACA
010
DACB
011
TACHA
100
TACHB
101
GPIO Data
110
GPIO Setup
111
Table 2. LTC1840 Register Address and Contents
Note 1: Number in ( )signifies default bit status upon power-up.
Note 2: State of bit depends on slave address used.
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