參數(shù)資料
型號(hào): LTC1778-1
廠商: Linear Technology Corporation
英文描述: Wide Operating Range, No RSENSE Step-Down Controller
中文描述: 寬工作,無(wú)檢測(cè)電阻范圍步降控制器
文件頁(yè)數(shù): 16/24頁(yè)
文件大?。?/td> 303K
代理商: LTC1778-1
16
LTC1778/LTC1778-1
1778fa
reduces the start delay while allowing C
SS
to charge up
slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, C
SS
is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8
μ
A cur-
rent then begins discharging C
SS
. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the soft-start
timing capacitor C
SS
be made large enough to guarantee
that the output is in regulation by the time C
SS
has reached
the 4V threshold. In general, this will depend upon the size
of the output capacitance, output voltage and load current
characteristic. A minimum soft-start capacitor can be
estimated from:
C
SS
> C
OUT
V
OUT
R
SENSE
(10
–4
[F/V s])
Generally 0.1
μ
F is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a short-
circuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5
μ
A to the RUN/SS pin. The additional
current prevents the discharge of C
SS
during a fault and
also shortens the soft-start period. Using a resistor to V
IN
as shown in Figure 8a is simple, but slightly increases
shutdown current. Connecting a resistor to INTV
CC
as
shown in Figure 8b eliminates the additional shutdown
current, but requires a diode to isolate C
SS
. Any pull-up
network must be able to pull RUN/SS above the 4.2V
maximum threshold of the latchoff circuit and overcome
the 4
μ
A maximum discharge current.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC1778 circuits:
1. DC I
2
R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I
2
R
loss. For example, if R
DS(ON)
= 0.01
and R
L
= 0.005
, the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V and can be estimated from:
Transition Loss
(1.7A
–1
) V
IN2
I
OUT
C
RSS
f
3. INTV
CC
current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTV
CC
current through the EXTV
CC
pin from a high
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. C
IN
loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
APPLICATIOU
W
U
U
Figure 8. RUN/SS Pin Interfacing with Latchoff Defeated
3.3V OR 5V
RUN/SS
V
IN
INTV
CC
RUN/SS
D1
(8a)
(8b)
D2*
C
SS
R
SS
*
C
SS
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
R
SS
*
1778 F08
2N7002
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