參數(shù)資料
型號: LTC1750CFW#TRPBF
廠商: Linear Technology
文件頁數(shù): 1/20頁
文件大小: 0K
描述: IC ADC 14BIT 80MSPS SMPL 48TSSOP
標準包裝: 1,800
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 1.69W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應商設備封裝: 48-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
1
LTC1750
1750f
14-Bit, 80Msps
Wide Bandwidth ADC
s
Sample Rate: 80Msps
s
500MHz Full Power Bandwidth S/H
s
Direct IF Sampling Up to 500MHz
s
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
s
75.5dB SNR and 90dB SFDR (PGA = 0)
s
73dB SNR and 90dB SFDR (PGA = 1)
s
No Missing Codes
s
Single 5V Supply
s
Power Dissipation: 1.45W
s
Two Pin Selectable Reference Values
s
Two’s Complement or Offset Binary Outputs
s
Out-of-Range Indicator
s
Data Ready Output Clock
s
Pin-for-Pin Family
s
48-Pin TSSOP Package
s
Telecommunications
s
Receivers
s
Cellular Base Stations
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Spectrum Analysis
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Imaging Systems
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MRI
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Tomography
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
1750 is an 80Msps, 14-bit A/D converter de-
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1750 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 82dB with an
input frequency of 250MHz. Ultralow jitter of 0.12psRMS
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include
±3LSB INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
80Msps, 14-Bit ADC with a 2.25V Differential Input Range
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
BLOCK DIAGRA
W
OF
14-BIT
PIPELINED ADC
14
S/H
CIRCUIT
±1.125V
DIFFERENTIAL
ANALOG INPUT
AIN
+
PGA
AIN
SENSE
VCM
4.7
F
DIFF AMP
REFLA
REFHB
GND
1750 BD
ENC
4.7
F
1
F1F
0.1
F
0.1
F
REFHA
REFLB
BUFFER
RANGE
SELECT
2VREF
CORRECTION
LOGIC AND
SHIFT
REGISTER
OUTPUT
LATCHES
CONTROL LOGIC
OVDD
VDD
OGND
0.5V TO 5V
5V
0.1
F
1
F
1
F
1
F
D13
D0
CLKOUT
ENC
DIFFERENTIAL
ENCODE INPUT
MSBINV
0.1
F
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