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參數(shù)資料
| 型號(hào)： | LTC1748CFW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80Msps Low Noise ADC |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, TSSOP-48 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大?。?/td> | 533K |
| 代理商： | LTC1748CFW |
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LTC1748
1748fa
14-Bit, 80Msps Low Noise ADC
I
Sample Rate: 80Msps
I
76.3dB SNR and 90dB SFDR (3.2V Range)
I
72.6dB SNR and 90dB SFDR (2V Range)
I
No Missing Codes
I
I
Power Dissipation: 1.4W
I
Selectable Input Ranges:
±
1V or
±
1.6V
I
240MHz Full Power Bandwidth S/H
I
Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
I
48-Pin TSSOP Package
I
Telecommunications
I
Receivers
I
Cellular Base Stations
I
Spectrum Analysis
I
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
1748 is an 80Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of
±
1V
and
±
1.6V along with a resistor programmable mode
allow the LTC1748’s input range to be optimized for a wide
variety of applications.
The LTC1748 is perfect for demanding communications
applications with AC performance that includes 76.3dB
SNR and 90dB spurious free dynamic range. Ultralow jitter
of 0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance. DC specs include
±
3LSB INL
and no missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
80Msps, 14-Bit ADC with a 2V Differential Input Range
14-BIT
PIPELINED ADC
14
S/H
AMP
±
1V
DIFFERENTIAL
ANALOG INPUT
A
IN+
A
IN–
SENSE
V
CM
4.7
μ
F
DIFF AMP
REFLA
REFHB
GND
1748 BD
ENC
4.7
μ
F
1
μ
F
1
μ
F
0.1
μ
F
0.1
μ
F
REFHA
REFLB
BUFFER
RANGE
SELECT
2.35V
REF
CORRECTION
LOGIC AND
SHIFT
REGISTER
OUTPUT
LATCHES
CONTROL LOGIC
OV
DD
V
DD
OGND
0.5V
TO 5V
5V
0.1
μ
F
1
μ
F
1
μ
F
1
μ
F
D13
D0
CLKOUT
OF
ENC
DIFFERENTIAL
ENCODE INPUT
OE
MSBINV
0.1
μ
F
DESCRIPTIOU
FEATURES
APPLICATIU
BLOCK DIAGRA
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