參數(shù)資料
    型號(hào): LTC1745
    廠商: Linear Technology Corporation
    英文描述: 14-Bit, 80Msps Low Power 3V ADC
    中文描述: 14位,80Msps ADC的低功耗3V的
    文件頁(yè)數(shù): 5/20頁(yè)
    文件大小: 464K
    代理商: LTC1745
    LTC2249
    5
    2249f
    Note 1:
    Absolute Maximum Ratings are those values beyond which the life
    of a device may be impaired.
    Note 2:
    All voltage values are with respect to ground with GND and OGND
    wired together (unless otherwise noted).
    Note 3:
    When these pin voltages are taken below GND or above V
    DD
    , they
    will be clamped by internal diodes. This product can handle input currents
    of greater than 100mA below GND or above V
    DD
    without latchup.
    Note 4:
    V
    DD
    = 3V, f
    SAMPLE
    = 80MHz, input range = 2V
    P-P
    with differential
    drive, unless otherwise noted.
    Note 5:
    Integral nonlinearity is defined as the deviation of a code from a
    straight line passing through the actual endpoints of the transfer curve.
    The deviation is measured from the center of the quantization band.
    Note 6:
    Offset error is the offset voltage measured from –0.5 LSB when
    the output code flickers between 00 0000 0000 0000 and
    11 1111 1111 1111.
    Note 7:
    Guaranteed by design, not subject to test.
    Note 8:
    V
    DD
    = 3V, f
    SAMPLE
    = 80MHz, input range = 1V
    P-P
    with
    differential drive.
    Note 9:
    Recommended operating conditions.
    TIW
    range, otherwise specifications are at T
    A
    = 25
    °
    C. (Note 4)
    The
    denotes the specifications which apply over the full operating temperature
    SYMBOL
    f
    s
    t
    L
    PARAMETER
    Sampling Frequency
    CLK Low Time
    CONDITIONS
    (Note 9)
    Duty Cycle Stabilizer Off
    Duty Cycle Stabilizer On (Note 7)
    Duty Cycle Stabilizer Off
    Duty Cycle Stabilizer On (Note 7)
    MIN
    1
    5.9
    5
    5.9
    5
    TYP
    MAX
    80
    500
    500
    500
    500
    UNITS
    MHz
    6.25
    6.25
    6.25
    6.25
    0
    2.7
    4.3
    3.3
    6
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    t
    H
    CLK High Time
    t
    AP
    t
    D
    Sample-and-Hold Aperture Delay
    CLK to DATA Delay
    Data Access Time After OE
    BUS Relinquish Time
    C
    L
    = 5pF (Note 7)
    C
    L
    = 5pF (Note 7)
    (Note 7)
    1.4
    5.4
    10
    8.5
    Pipeline
    Latency
    Cycles
    Typical DNL, 2V Range
    Typical INL, 2V Range
    8192 Point FFT, f
    IN
    = 5MHz,
    –1dB, 2V Range
    TYPICAL PERFOR U
    CODE
    0
    I
    0
    0.5
    1.0
    16384
    2249 G01
    –0.5
    –1.0
    –2.0
    4096
    8192
    12288
    –1.5
    2.0
    1.5
    CODE
    0
    D
    0.2
    0.4
    0.6
    16384
    2249 G02
    0
    –0.2
    –1.0
    4096
    8192
    12288
    –0.6
    –0.4
    –0.8
    1.0
    0.8
    FREQUENCY (MHz)
    0
    A
    –60
    –70
    –40
    –50
    –20
    –30
    0
    35
    2249 G03
    –80
    –90
    –100
    –110
    –120
    –10
    5
    15
    25
    10
    20
    30
    40
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