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參數(shù)資料
| 型號： | LTC1744IFW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 50MSPS 48-TSSOP |
| 標準包裝： | 1,800 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.5W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 其它名稱： | LTC1744IFWTR |
12
LTC1744
1744f
APPLICATIO S I FOR ATIO
WU
U
Figure 1. Block Diagram
DIFF
REF
AMP
REF
BUF
4.7
F
1
F
0.1
F
0.1
F
1
F
INTERNAL CLOCK SIGNALS
REFL
REFH
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
2.5V
REFERENCE
5-BIT
PIPELINED
ADC STAGE
FIRST STAGE
4-BIT
PIPELINED
ADC STAGE
SECOND STAGE
4-BIT
PIPELINED
ADC STAGE
THIRD STAGE
4-BIT
FLASH
ADC
FOURTH STAGE
ENC
REFHA
REFLB
REFLA REFHB
ENC
SHIFT REGISTER
AND CORRECTION
OE
MSBINV
OGND
OF
OVDD 0.5V TO
5V
D13
D0
CLKOUT
1744 F01
INPUT
S/H
SENSE
VCM
AIN
–
AIN
+
4.7
F
OUTPUT
DRIVERS
CONTROL LOGIC
AND
CALIBRATION LOGIC
The LTC1744 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample Hold Operation
Figure 2 shows an equivalent circuit for the LTC1744
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in lowest possible noise for a
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| LTC1745CFW#PBF | 功能描述:IC ADC 12BIT 25MSPS LN 48TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| LTC1745CFW#TR | 功能描述:IC ADC SMPL 12BIT 25MSPS 48TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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