參數(shù)資料
    型號: LTC1742CFW
    廠商: Linear Technology
    文件頁數(shù): 1/20頁
    文件大小: 0K
    描述: IC ADC 14BIT 65MSPS 48-TSSOP
    標準包裝: 39
    位數(shù): 14
    采樣率(每秒): 65M
    數(shù)據(jù)接口: 并聯(lián)
    轉(zhuǎn)換器數(shù)目: 1
    功率耗散(最大): 1.38W
    電壓電源: 單電源
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
    供應(yīng)商設(shè)備封裝: 48-TSSOP
    包裝: 管件
    輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
    1
    LTC1742
    1742f
    14-Bit, 65Msps Low Noise ADC
    s
    Sample Rate: 65Msps
    s
    76.5dB SNR and 90dB SFDR (3.2V Range)
    s
    72.8dB SNR and 90dB SFDR (2V Range)
    s
    No Missing Codes
    s
    Single 5V Supply
    s
    Power Dissipation: 1.275W
    s
    Selectable Input Ranges:
    ±1V or ±1.6V
    s
    240MHz Full Power Bandwidth S/H
    s
    Pin Compatible Family
    25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
    50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
    65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
    80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
    s
    48-Pin TSSOP Package
    s
    Telecommunications
    s
    Receivers
    s
    Cellular Base Stations
    s
    Spectrum Analysis
    s
    Imaging Systems
    , LTC and LT are registered trademarks of Linear Technology Corporation.
    The LTC
    1742 is an 65Msps, sampling 14-bit A/D con-
    verter designed for digitizing high frequency, wide dy-
    namic range signals. Pin selectable input ranges of
    ±1V
    and
    ±1.6V along with a resistor programmable mode
    allow the LTC1742’s input range to be optimized for a wide
    variety of applications.
    The LTC1742 is perfect for demanding communications
    applications with AC performance that includes 76.5dB
    SNR and 90dB spurious free dynamic range. Ultralow jitter
    of 0.15psRMS allows undersampling of IF frequencies with
    excellent noise performance. DC specs include
    ±3LSBINL
    and
    ±1LSB DNL.
    The digital interface is compatible with 5V, 3V, 2V and
    LVDS logic levels. The ENC and ENC inputs may be driven
    differentially from PECL, GTL and other low swing logic
    families or from single-ended TTL or CMOS. The low
    noise, high gain ENC and ENC inputs may also be driven
    by a sinusoidal signal without degrading performance. A
    separate output power supply can be operated from 0.5V
    to 5V, making it easy to connect directly to low voltage
    DSPs or FIFOs.
    The TSSOP package with a flow-through pinout simplifies
    the board layout.
    65Msps, 14-Bit ADC with a 2V Differential Input Range
    14-BIT
    PIPELINED ADC
    14
    S/H
    AMP
    ±1V
    DIFFERENTIAL
    ANALOG INPUT
    AIN
    +
    AIN
    SENSE
    VCM
    4.7
    F
    DIFF AMP
    REFLA
    REFHB
    GND
    1742 BD
    ENC
    4.7
    F
    1
    F1F
    0.1
    F
    0.1
    F
    REFHA
    REFLB
    BUFFER
    RANGE
    SELECT
    2.35VREF
    CORRECTION
    LOGIC AND
    SHIFT
    REGISTER
    OUTPUT
    LATCHES
    CONTROL LOGIC
    OVDD
    VDD
    OGND
    0.5V
    TO 5V
    5V
    0.1
    F
    1
    F
    1
    F
    1
    F
    D13
    D0
    CLKOUT
    OF
    ENC
    DIFFERENTIAL
    ENCODE INPUT
    OE
    MSBINV
    0.1
    F
    DESCRIPTIO
    U
    FEATURES
    APPLICATIO S
    U
    BLOCK DIAGRA
    W
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