參數(shù)資料
型號: LTC1664IGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC D/A CONV 10BIT QUAD 16-SSOP
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時間: 6µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 1mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
LTC1664
10
1664fa
operation
load can be successfully driven by inserting a 20Ω resis-
tor; a 2.2F load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 3c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
1664 F03
INPUT CODE
(3b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
512
0
1023
INPUT CODE
OUTPUT
VOLTAGE
(3a)
VREF = VCC
(3c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When VREF = VCC
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