timing characteristics The l denotes the specifications which apply over the full oper" />
參數(shù)資料
型號(hào): LTC1664CGN#PBF
廠商: Linear Technology
文件頁數(shù): 11/16頁
文件大小: 0K
描述: IC DAC 10BIT QUAD MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝: 100
設(shè)置時(shí)間: 6µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 1mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1350 (CN2011-ZH PDF)
LTC1664
4
1664fa
timing characteristics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
l
40
ns
t2
DIN Valid to SCK Hold
l
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
80
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
80
ns
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
80
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
20
ns
t10
CLR Pulse Width
(Note 6)
l
100
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
(Notes 6 and 8)
l
16.7
MHz
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
l
60
ns
t2
DIN Valid to SCK Hold
(Note 6)
l
0
ns
t3
SCK High Time
(Note 6)
l
50
ns
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
100
ns
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
150
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
30
ns
t10
CLR Pulse Width
(Note 6)
l
120
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
(Notes 6 and 8)
l
10
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined and tested at
VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See the Rail-to-Rail
Output Considerations section.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V.
Note 6: Guaranteed by design and not subject to test.
Note 7: Measured at code 20.
Note 8: If a continuous clock is used, CS/LD timing (t7 and t9) will limit
the maximum clock frequency to 5MHz at 4.5V to 5.5V (3.85MHz at 2.7V
to 5.5V).
Note 9: Any output shorted.
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