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參數(shù)資料
| 型號(hào)： | LTC1663IMS8#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT R-R MICROPWR 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 630µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
LTC1663
5
1663fd
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation vs Output Current
Offset Error Voltage vs
Temperature
Full-Scale Output Voltage vs
Temperature
IOUT (mA)
–1.0
Δ
V
OUT
(LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–0.6 –0.4
0
0.2
1663 G07
–0.6
0.6
0.8
0.2
–0.8
–0.2
0.6
0.4
0.8 1.0
VCC = VREF = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
SOURCE
SINK
TEMPERATURE (°C)
–60
OFFSET
ERROR
VOLTAGE
(mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
–20
20
40
1663 G08
–40
0
60
80
100
TEMPERATURE (°C)
–60
OUTPUT
VOLTAGE
(V)
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
–20
20
40
1663 G09
–40
0
60
80
100
REFERENCE SET TO
INTERNAL BANDGAP
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged
by the SDA pin. High impedance pin while data is shifted
in. Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.
Data is shifted into the SDA pin at the rising edges of the
clock. This high impedance pin requires a pull-up resistor
or current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔVOUT – LSB)/LSB
Where ΔVOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the ana-
log output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specied
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
DEFINITIONS
PIN FUNCTIONS
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