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參數(shù)資料
| 型號(hào)： | LTC1662CN8 |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL ULT LPWR 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 400µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 260µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
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LTC1662
10
1662fa
operation
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10-bit input register and 10-bit DAC register.
Byselectingtheappropriate4-bitcontrolcode(seeTable1)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the SDI input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit input code, D9-D0, ordered MSB to LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table1. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special sleep
instruction (see Table 1). In this mode, static power
consumption is greatly reduced. The reference input and
analog outputs are set in a high impedance state and all
DAC settings are retained in memory so that when sleep
mode is exited, the outputs of DACs not updated by the
Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during sleep (control codes 0001b
and 0010b); then, a single command (1000b) can be used
both to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001b is used to load DAC A
duringsleep.Thencontrolcode0101bloadsDACB,wakes
the part and simultaneously updates both DAC outputs.
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in
the LTC1662 can typically source or sink at least 1mA
(VCC=5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 130Ω (typical) when driving a load to
therails.Theoutputamplifiersarestabledrivingcapacitive
loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. Please
see the Output Minimum Resistance vs Load Capacitance
curve in the Typical Performance Characteristics section.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE = VOS + GE) is positive, the output for the highest
codes limits at VCC as shown in Figure 2c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
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