參數(shù)資料
型號(hào): LTC1658CMS8#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 0K
描述: IC D/A CONV 14BIT R-R 8-MSOP
標(biāo)準(zhǔn)包裝: 50
設(shè)置時(shí)間: 12µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 3mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1350 (CN2011-ZH PDF)
5
LTC1658
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Broadband Noise
TEMPERATURE (
°C)
–55
–25
5
35
65
95
125
GAIN
ERROR
(LSB)
1658 G06
5
4
3
2
1
0
–1
–2
–3
–4
–5
Gain Error vs Temperature
BW = 1Hz TO
200
s/DIV
1658 G08
100kHz
PIN FUNCTIONS
UU
U
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
DIN (Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1658 requires a 16-bit word to be loaded in.
The last two bits are don’t cares.
CS/LD (Pin 3): The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
DOUT (Pin 4): Output of the Shift Register Which Becomes
Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
REF (Pin 6): Reference Input. There is a gain of one from
this pin to the output. When tied to VCC the output will
swing from GND to VCC. The output can only swing to
within it’s offset specification of VCC (see Applicatons
Information).
VOUT (Pin 7): Buffered Rail-to-Rail DAC Output.
VCC (Pin 8): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
1LSB/DIV
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