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參數資料
| 型號： | LTC1654IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package |
| 中文描述： | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 154K |
| 代理商： | LTC1654IGN |
6
LTC1654
Serial Interface
The data on the SDI input is loaded into the shift register
on the rising edge of SCK. The MSB is loaded first. The
Clock is disabled internally when CS/LD is high. Note:
SCK must be low before CS/LD is pulled low to avoid an
extra internal clock pulse.
If no daisy-chaining is required, the input word can be
24-bit wide, as shown in the timing diagrams. The 8 MSBs,
which are loaded first, are the control and address bits
followed by a 16-bit data word. The last two LSBs in the
data word are don’t cares. The input word can be a stream
of three 8-bit wide segments as shown in the “24-Bit
Update” timing diagram.
If daisy-chaining is required or if the input needs to be
written in two 16-bit wide segments, then the input word
can be 32 bits wide and the top 8 bits (MSBs) are don’t
cares. The remaining 24 bits are control/address and
data. This is also shown in the timing diagrams. The
buffered output of the internal 32-bit shift register is
available on the SDO pin, which swings from GND to V
CC
.
Multiple LTC1654s may be daisy-chained together by
connecting the SDO pin to the SDI pin of the next IC. The
SCK and CS/LD signals remain common to all ICs in the
daisy-chain. The serial data is clocked to all of the chips,
then the CS/LD signal is pulled high to update all DACs
simultaneously.
Table 1 shows the truth table for the control/address bits.
When the supplies are first applied, the LTC1654 uses
SLOW mode, the outputs are set at 0V, and zeros are
loaded into the 32-bit input shift register. Three examples
are given to illustrate the DAC’s operation:
1.
Load and update DAC A in FAST mode. Leave DAC B
unchanged.
Perform the following sequence for the
control, address and DATA bits:
Step 1: Set DAC A in FAST mode
CS/LD
clock in 0101 0000 XXXXXXXX XXXXXXXX;
CS/LD
Step 2: Load and update DAC A with DATA
CS/LD
clock in 0011 0000 + DATA; CS/LD
2.
Load and update DAC A in SLOW mode. Power down
DAC B.
Perform the following sequence for the control,
address and DATA bits:
Step 1: Set DAC A in SLOW mode
CS/LD
clock in 0110 0000 XXXXXXXX XXXXXXXX;
CS/LD
Step 2: Load and update DAC A with DATA
CS/LD
Step 3: Power down DAC B
CS/LD
clock in 0100 0001 XXXXXXXX XXXXXXXX;
CS/LD
3.
Power down both DACs at the same time.
Perform the
following sequence for the control, address and DATA
bits:
Step 1: Power down both DACs simultaneously
CS/LD
clock in 0100 1111 XXXXXXXX XXXXXXXX;
CS/LD
clock in 0011 0000 + DATA; CS/LD
Voltage Output
The LTC1654 comes complete with rail-to-rail voltage
output buffer amplifiers. These amplifiers will swing to
within a few millivolts of either supply rail when unloaded
and to within a 300mV of either supply rail when sinking
or sourcing 5mA.
There are two GAIN configuration modes for the LTC1654:
a) GAIN of 1: (X
1
/X
1/2
tied to REFLO)
V
OUT
= (V
REFHI
– V
REFLO
)(SDI/16384) + V
REFLO
b) GAIN of 1/2: (X
1
/X
1/2
tied to V
OUT
)
V
OUT
= (1/2)(V
REFHI
– V
REFLO
)(SDI/16384) + V
REFLO
The LTC 1654 has two SPEED modes: A FAST mode and
a SLOW mode. When operating in the FAST mode, the
output amplifiers will settle in 3.5
μ
s (typ) to 14 bits on a
4V output swing. In the SLOW mode, they will settle in
8
μ
s. The total supply current is 750
μ
A in the FAST mode
and 450
μ
A in the SLOW mode.
OPERATIOU
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