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參數(shù)資料
| 型號： | LTC1650ACS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Low Power Timer 8-SOIC -40 to 125 |
| 中文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 253K |
| 代理商： | LTC1650ACS |
9
LTC1650
OPERATIOU
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one
16-bit word, MSB first. The DAC register loads the data
from the shift register when CS/LD is pulled high. The
clock is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 16-bit shift register is available
on the D
OUT
pin which swings from DGND to DV
DD
.
Multiple LTC1650s may be daisy-chained together by
connecting the D
OUT
pin to the D
IN
pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the CS/LD signal is pulled high to update all
of them simultaneously.
When CLR is pulled low or when the part powers up, the
output connects through an internal pass gate to V
RST
and
will go to whatever voltage is on V
RST
. When any of three
supplies (DV
DD
, AV
DD
, |AV
SS
|) goes below 2.5V, the
RSTOUT pin goes low and stays low as long as the supply
is below 2.5V. The power-on reset is also activated when
one of the supplies drops below 2.5V and the output is
then connected to V
RST
. The output connects to V
RST
when any of three conditions occur: CLR goes low, the part
powers up or one of the supplies drops below 2.5V. This
condition exists as long as CS/LD is low. As soon as CS/
LD goes high, the DAC register is loaded with the data in
the shift register and the output will settle to its new value.
Voltage Output
The LTC1650 rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range. The
output can swing to within a few millivolts of either supply
rail when unloaded and has an equivalent output resis-
tance of 50
when driving a load to the rails. The buffer
amplifier can drive 1000pF without going into oscillation.
The LTC1650 has a deglitched voltage output. The midscale
glitch is less than 2nV-s. The digital feedthrough is about
0.05nV-s.
Output Ranges
The LTC1650 is capable of unipolar or bipolar output
swing. When the UNI/BIP pin is connected to V
OUT
the part
is configured for unipolar operation and the output will
swing from REFLO to REFHI. When UNI/BIP is connected
to REFHI the part is configured in bipolar mode and the
output will swing from (2 REFLO – REFHI) to REFHI and
will be at REFLO at midscale. With REFLO = 0V the output
swing is
±
REFHI in bipolar mode and 0V to REFHI in
unipolar mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1650AIN | Low Glitch 16-Bit Voltage Output DAC |
| LTC1650AIS | Automotive Catalog LinCMOS TIMER 8-SOIC -40 to 125 |
| LTC1650C | Low Power LinCMOS<TM> Timer 20-LCCC -55 to 125 |
| LTC1650CN | Low Power LinCMOS<TM> Timer 8-CDIP -55 to 125 |
| LTC1650I | Low Power LinCMOS<TM> Timer 8-CDIP -55 to 125 |
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