The data on the DIN input is loaded into the shift register<" />
參數(shù)資料
型號(hào): LTC1650ACS#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 12/12頁(yè)
文件大小: 0K
描述: IC D/A CONV 16BIT R-R 16-SOIC
標(biāo)準(zhǔn)包裝: 50
設(shè)置時(shí)間: 4µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 50mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1350 (CN2011-ZH PDF)
9
LTC1650
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one
16-bit word, MSB first. The DAC register loads the data
from the shift register when CS/LD is pulled high. The
clock is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 16-bit shift register is available
on the DOUT pin which swings from DGND to DVDD.
Multiple LTC1650s may be daisy-chained together by
connecting the DOUT pin to the DIN pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the CS/LD signal is pulled high to update all
of them simultaneously.
When CLR is pulled low or when the part powers up, the
output connects through an internal pass gate to VRST and
will go to whatever voltage is on VRST. When any of three
supplies (DVDD, AVDD, |AVSS|) goes below 2.5V, the
RSTOUT pin goes low and stays low as long as the supply
is below 2.5V. The power-on reset is also activated when
one of the supplies drops below 2.5V and the output is
then connected to VRST. The output connects to VRST
when any of three conditions occur: CLR goes low, the part
powers up or one of the supplies drops below 2.5V. This
condition exists as long as CS/LD is low. As soon as CS/LD
goes high, the DAC register is loaded with the data in the
shift register and the output will settle to its new value.
Voltage Output
The LTC1650 rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range. The
output is specified to swing up to
±4.5V on ±4.75V
supplies with VOUT unloaded. (For typical output swing at
various load currents, refer to the typical curve “Minimum
Supply Headroom for Full Output Swing vs Load Cur-
rent.”) The buffer amplifier can drive 1000pF without
going into oscillation. The LTC1650 has a deglitched
voltage output. The midscale glitch is less than 2nV-s. The
digital feedthrough is about 0.05nV-s.
Output Ranges
The LTC1650 is capable of unipolar or bipolar output
swing. When the UNI/BIP pin is connected to VOUT the part
is configured for unipolar operation and the output will
swing from REFLO to REFHI. When UNI/BIP is connected
to REFHI the part is configured in bipolar mode and the
output will swing from (2 REFLO – REFHI) to REFHI and
will be at REFLO at midscale. With REFLO = 0V the output
swing is
±REFHI in bipolar mode and 0V to REFHI in
unipolar mode.
OPERATIO
U
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