參數(shù)資料
型號(hào): LTC1646
廠商: Linear Technology Corporation
英文描述: Low Power Timer 8-PDIP 0 to 70
中文描述: 負(fù)48V熱插拔控制器
文件頁數(shù): 7/12頁
文件大?。?/td> 230K
代理商: LTC1646
7
LT4250L/LT4250H
4250lhf
APPLICATIO
S I
N
FOR
ATIO
U
Hot Circuit Insertion
When circuit boards are inserted into a live –48V backplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
The LT4250 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
W
U
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the V
EE
pin of the LT4250). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the inrush current charging load capacitors C3 and
C4 can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The C2 capacitor can
be calculated with the following equation:
C2 = (45
μ
A C
L
)/I
INRUSH
where C
L
is the total load capacitance = C3 + C4 + module
input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to V
EE
C2/C
GS(Q1)
before the
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
C
V
V
V
C
C
INMAX
TH
TH
GD
1
2
=
+
(
)
C1
35 C2 for V
INMAX
= 72V
where V
TH
is the MOSFET’s minimum gate threshold and
V
INMAX
is the maximum operating input voltage.
R3 should not exceed a value that produces an
R3 C2 time-constant of 150
μ
s. A 1k value for R3 will
ensure this for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
Figure 6a. Inrush Control Circuitry
+
V
EE
V
DD
LT4250H
PWRGD
UV = 38.5V
OV = 71V
SENSE
C1
470nF
25V
C3
0.1
μ
F
100V
C4
100
μ
F
100V
C5
100
μ
F
16V
Q1
IRF530
R2
10
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02
5%
4
3
2
OV
–48V RTN
–48V RTN
(SHORT PIN)
–48V
UV
5
6
8
7
1
GATE
DRAIN
VICOR
VI-J30-CY
V
IN+
V
OUT+
V
OUT–
5V
4250 F06a
GATE IN
V
IN–
+
*
* DIODES INC. SMAT70A
4
3
2
1
Figure 6b. Inrush Control Waveforms
INRUSH
CURRENT
500mA/DIV
GATE –V
EE
10V/DIV
DRAIN
50V/DIV
V
EE
50V/DIV
25ms/DIV
4250 F06b
BOUNCE
MODULE
TURN-ON
MODULE
TURN-ON
CONTACT
相關(guān)PDF資料
PDF描述
LT4250H Negative 48V Hot Swap Controller
LT4250HCN8 Negative 48V Hot Swap Controller
LT4250HCS8 Negative 48V Hot Swap Controller
LT4250L Negative 48V Hot Swap Controller
LT4250LCN8 Negative 48V Hot Swap Controller
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