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參數(shù)資料
| 型號(hào)： | LTC1608CG#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 17/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 16BIT SAMPLNG 36SSOP |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 420mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 1347 (CN2011-ZH PDF) |
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6
LTC1608
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
difference voltage between AIN+ and AIN– with a differen-
tial range of
±2.5V. AIN+ has a ±2.5V input range when
AIN– is grounded.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with AIN+.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with
2.2
F tantalum in parallel with 0.1F ceramic.
REFCOMP (Pin 4): 4.375V (Nominal) Reference Compen-
sation Pin. Bypass to AGND with 22
F tantalum in parallel
with 0.1
F ceramic. This is not recommended for use as
an external reference due to part-to-part output voltage
variations and glitches that occur during the conversion.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10
F tantalum in parallel with 0.1F ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10
F tantalum in parallel with 0.1F
ceramic.
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
CS (Pin 32): The Chip Select Input. Must be low for the ADC
to recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
VSS (Pin 34): –5V Negative Supply. Bypass to AGND with
10
F tantalum in parallel with 0.1F ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1F ceramic.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1F ceramic and
connect this pin to Pin 35 with a 10
resistor.
UU
U
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Intermodulation Distortion
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
FREQUENCY (kHz)
0
–40
–20
0
200
1608 G07
–60
–80
50
100
150
250
–100
–120
–140
AMPLITUDE
(dB)
fSAMPLE = 500kHz
fIN1 = 96.56kHz
fIN2 = 99.98kHz
INPUT FREQUENCY (Hz)
1k
AMPLITUDE
OF
POWER
SUPPLY
FEEDTHROUGH
(dB)
0
–20
–40
–60
–80
–100
–120
–140
10k
100k
1M
1608 G08
fSAMPLE = 500kHz
VRIPPLE = 10mV
VSS
AVDD
INPUT FREQUENCY (Hz)
1k
COMMON
MODE
REJECTION
(dB)
80
70
60
50
40
30
20
10
0
10k
100k
1608 G14a
1M
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