AIN + CSMPL HOLD SAMPLE
  • 參數資料
    型號: LTC1608AIG
    廠商: Linear Technology
    文件頁數: 19/20頁
    文件大?。?/td> 0K
    描述: IC CONV A/D 16BIT 500KSPS 36SSOP
    標準包裝: 37
    位數: 16
    采樣率(每秒): 500k
    數據接口: 并聯(lián)
    轉換器數目: 1
    功率耗散(最大): 420mW
    電壓電源: 模擬和數字,雙 ±
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
    供應商設備封裝: 36-SSOP
    包裝: 管件
    輸入數目和類型: 2 個單端,雙極;1 個差分,雙極
    8
    LTC1608
    +
    COMP
    AIN
    +
    CSMPL
    HOLD
    SAMPLE
    AIN
    CSMPL
    +CDAC
    +VDAC
    –CDAC
    –VDAC
    HOLD
    SAMPLE
    HOLD
    SAR
    OUTPUT
    LATCHES
    16
    D15
    D0
    1608 F01
    ZEROING SWITCHES
    Figure 1. Simplified Block Diagram
    compared with the binary-weighted charges supplied by
    the differential capacitive DAC. Bit decisions are made by
    the high speed comparator. At the end of a conversion, the
    differential DAC output balances the AIN+ and AIN– input
    charges. The SAR contents (a 16-bit data word) which
    represent the difference of AIN+ and AIN– are loaded into
    the 16-bit output latches.
    DIGITAL INTERFACE
    The A/D converter is designed to interface with micropro-
    cessors as a memory mapped device. The CS and RD
    control inputs are common to all peripheral memory
    interfacing. A separate CONVST is used to initiate a con-
    version.
    Internal Clock
    The A/D converter has an internal clock that runs the A/D
    conversion. The internal clock is factory trimmed to achieve
    a typical conversion time of 1.45
    s and a maximum
    conversion time of 1.8
    s over the full temperature range.
    No external adjustments are required. The guaranteed
    maximum acquisition time is 400ns. In addition, a through-
    put time (acquisition + conversion) of 2
    s and a minimum
    sampling rate of 500ksps are guaranteed.
    APPLICATIO S I FOR ATIO
    WU
    UU
    3V Input/Output Compatible
    The LTC1608 operates on
    ±5V supplies, which makes the
    device easy to interface to 5V digital systems. This device
    can also talk to 3V digital systems: the digital input pins
    (SHDN, CS, CONVST and RD) of the LTC1608 recognize
    3V or 5V inputs. The LTC1608 has a dedicated output
    supply pin (OVDD) that controls the output swings of the
    digital output pins (D0 to D15, BUSY) and allows the part
    to talk to either 3V or 5V digital systems. The output is
    two’s complement binary.
    Power Shutdown
    The LTC1608 provides two power shutdown modes, Nap
    and Sleep, to save power during inactive periods. The Nap
    mode reduces the power by 95% and leaves only the
    digital logic and reference powered up. The wake-up time
    from Nap to active is 200ns. In Sleep mode, all bias
    currents are shut down and only leakage current remains
    (about 1
    A). Wake-up time from Sleep mode is much
    longer since the reference circuit must power up and
    settle. Sleep mode wake-up time is dependent on the
    value of the capacitor connected to the REFCOMP (Pin 4).
    The wake-up time is 80ms with the recommended 22
    F
    capacitor.
    Shutdown is controlled by Pin 33 (SHDN). The ADC is in
    shutdown when SHDN is low. The shutdown mode is
    selected with Pin 32 (CS). When SHDN is low, CS low
    selects nap and CS high selects sleep.
    Figure 2a. Nap Mode to Sleep Mode Timing
    t3
    SHDN
    CS
    1608 F02a
    t4
    SHDN
    CONVST
    1608 F02b
    Figure 2b. SHDN to CONVST Wake-Up Timing
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