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參數(shù)資料
| 型號： | LTC1605-1CN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 5V SAMPLING 28DIP |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
| 配用： | DC1255A-A-ND - BOARD SAR ADC LTC1605 |
4
LTC1605-1/LTC1605-2
The q denotes the specifications which apply over the full operating temperature
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
100
kHz
tCONV
Conversion Time
q
8
s
tACQ
Acquisition Time
q
2
s
t1
Convert Pulse Width
(Note 11)
q
40
ns
t2
Data Valid Delay After R/C
↓
(Note 9)
q
8
s
t3
BUSY Delay from R/C
↓
CL = 50pF
q
65
ns
t4
BUSY Low
8
s
t5
BUSY Delay After End of Conversion
220
ns
t6
Aperture Delay
40
ns
t7
Bus Relinquish Time
q
10
35
83
ns
t8
BUSY Delay After Data Valid
q
50
200
ns
t9
Previous Data Valid After R/C
↓
7.4
s
t10
R/C to CS Setup Time
(Notes 9, 10)
10
ns
t11
Time Between Conversions
10
s
t12
Bus Access and Byte Delay
(Notes 9, 10)
10
83
ns
The q denotes the specifications which apply over the full operating temperature
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
(Notes 9, 10)
4.75
5.25
V
IDD
Positive Supply Current
q
11
16
mA
PDIS
Power Dissipation
55
80
mW
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VANA =
VDIG = VDD, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above VDD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a VIN input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Zero error for the LTC1605-1 is the voltage measured from
0.5LSB when the output code flickers between 0000 0000 0000 0000
and 0000 0000 0000 0001. Zero error for the LTC1605-2 is the voltage
measured from – 0.5LSB when the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 3
s after the
start of the conversion.
Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to
zero with external potentiometer.
Note 13: Full-scale error is the untrimmed deviation from ideal last code
transition, divided by the full-scale range and includes the effect of offset
error.
Note 14: All specifications in dB are referred to a full-scale 4V input for the
LTC1605-1 and to
±4V input for the LTC1605-2.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (
±20V) input
overvoltage for the LTC1605-1 and
±15V for the LTC1605-2.
TI I G CHARACTERISTICS
W
U
POWER REQUIRE E TS
W
U
range, otherwise specifications are at TA = 25°C. (Note 5)
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