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參數(shù)資料
| 型號： | LTC1604IG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-PDIP 0 to 70 |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO36 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LTC1604IG |
14
LTC1604
APPLICATIO
S I
FOR
ATIO
U
W
U
U
LTC1604
A
IN+
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
A
IN–
V
REF
REFCOMP
AGND
1604 F13
1
2
3
4
5
47
μ
F
LTC1450
2V TO 2.7V
Figure 14a. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)
1k
C
80
70
60
50
40
30
20
10
0
10k
100k
1604 G14a
1M
Figure 13. Driving V
REF
with a DAC
can not exceed the AV
DD
or V
SS
power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or –2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
LTC1604
A
IN+
A
IN–
V
REF
0V TO
5V
±
2.5V
REFCOMP
AGND
1604 F14b
1
2
3
4
5
10
μ
F
ANALOG INPUT
–
+
Figure 14b. Selectable 0V to 5V or
±
2.5V Input Range
Full-Scale and Offset Adjustment
Figure 15a shows the ideal input/output characteristics
for the LTC1604. The code transitions occur midway
between successive integer LSB values (i.e., –FS +
0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,
FS –
0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3
μ
V.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the A
IN–
input. For zero offset error apply
1604 F15a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
–(FS – 1LSB)
INPUT VOLTAGE (A
IN+
– A
IN–
)
O
Figure 15a. LTC1604 Transfer Characteristics
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1604ACG | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604AIG | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604C | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604 | High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown(高速，16位，333ksps采樣模數(shù)轉(zhuǎn)換器（帶關(guān)斷）) |
| LTC1605C | 16-Bit, 100ksps, Sampling ADC |
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