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參數(shù)資料
| 型號： | LTC1604CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-PDIP 0 to 70 |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO36 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LTC1604CG |
11
LTC1604
APPLICATIO
S I
FOR
ATIO
U
W
U
U
RD = CONVST
CS = 0
BUSY
1604 F08
t
CONV
t
6
DATA (N – 1)
D5 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
t
11
t
8
t
10
t
7
RD = CONVST
BUSY
CS = 0
1604 F09
t
CONV
t
6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
t
10
t
11
t
8
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
three-state until read by the MPU with the RD signal. Mode
2 can be used for operation with a shared data bus.
In slow memory and ROM modes (Figures 8 and 9) CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the com-
bined CONVST-RD signal. Conversions are started by the
MPU or DSP (no external sample clock is needed).
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (=CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
The differential analog inputs of the LTC1604 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the A
IN–
input is grounded). The A
IN+
and
A
IN–
inputs are sampled at the same instant. Any un-
wanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1604
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
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| LTC1604I | High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown |
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| LTC1604ACG | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604AIG | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604C | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
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