can not exceed the AVDD or VSS
參數(shù)資料
型號(hào): LTC1604CG#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 0K
描述: IC A/D CONV 16BIT SAMPLNG 36SSOP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 16
采樣率(每秒): 333k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 350mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
LTC1604
14
1604fa
can not exceed the AVDD or VSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common
mode voltage, however, the bipolar zero error (BZE) will
vary. The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or –2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
APPLICATIONS INFORMATION
LTC1604
AIN
+
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
AIN
VREF
REFCOMP
AGND
1604 F13
1
2
3
4
5
47μF
LTC1450
2V TO 2.7V
INPUT FREQUENCY (Hz)
1k
COMMON
MODE
REJECTION
(dB)
80
70
60
50
40
30
20
10
0
10k
100k
1604 G14a
1M
LTC1604
AIN
+
AIN
VREF
0V TO
5V
±2.5V
REFCOMP
AGND
1604 F14b
1
2
3
4
5
10μF
ANALOG INPUT
+
1604 F15a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
– (FS – 1LSB)
INPUT VOLTAGE (AIN
+ – AIN–)
OUTPUT
CODE
Figure 13. Driving VREF with a DAC
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range
Figure 15a. LTC1604 Transfer Characteristics
Figure 14a. CMRR vs Input Frequency
Full-Scale and Offset Adjustment
Figure 15a shows the ideal input/output characteristics
for the LTC1604. The code transitions occur midway
between successive integer LSB values (i.e., –FS +
0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,
FS – 0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3μV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale er-
ror adjustment. Zero offset is achieved by adjusting the
offset applied to the AIN– input. For zero offset error apply
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