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參數(shù)資料
| 型號： | LTC1604AIG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO36 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 378K |
| 代理商： | LTC1604AIG |
6
LTC1604
TYPICAL PERFOR
M
A
CE CHARACTERISTICS
U
INPUT FREQUENCY (Hz)
1k
C
80
70
60
50
40
30
20
10
0
10k
100k
1604G09
1M
Input Common Mode Rejection
vs Input Frequency
INPUT FREQUENCY (Hz)
1k
A
F
0
–20
–40
–60
–80
–100
–120
10k
100k
1M
1604 G07
f
SAMPLE
= 333kHz
V
RIPPLE
= 10mV
V
SS
A
VDD
Power Supply Feedthrough vs
Ripple Frequency
PI
FU
CTIO
N
S
U
U
A
IN+
(Pin 1):
Positive Analog Input. The ADC converts the
difference voltage between A
IN+
and A
IN–
with a differen-
tial range of
±
2.5V. A
IN+
has a
±
2.5V input range when
A
IN–
is grounded.
A
IN–
(Pin 2):
Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with A
IN+
.
V
REF
(Pin 3):
2.5V Reference Output. Bypass to AGND with
2.2
μ
F tantalum in parallel with 0.1
μ
F ceramic.
REFCOMP (Pin 4):
4.375 Reference Compensation Pin.
Bypass to AGND with 47
μ
F tantalum in parallel with 0.1
μ
F
ceramic.
AGND (Pins 5 to 8):
Analog Grounds. Tie to analog ground
plane.
DV
DD
(Pin 9):
5V Digital Power Supply. Bypass to DGND
with 10
μ
F tantalum in parallel with 0.1
μ
F ceramic.
DGND (Pin 10):
Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26):
Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27):
The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
OGND (Pin 28):
Digital Ground for Output Drivers.
OV
DD
(Pin 29):
Digital Power Supply for Output Drivers.
Bypass to OGND with 10
μ
F tantalum in parallel with 0.1
μ
F
ceramic.
RD (Pin 30):
Read Input. A logic low enables the output
drivers when CS is low.
CONVST (Pin 31):
Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
CS (Pin 32):
The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.
SHDN (Pin 33):
Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
V
SS
(Pin 34):
–5V Negative Supply. Bypass to AGND with
10
μ
F tantalum in parallel with 0.1
μ
F ceramic.
AV
DD
(Pin 35):
5V Analog Power Supply. Bypass to AGND
with 10
μ
F tantalum in parallel with 0.1
μ
F ceramic.
AV
DD
(Pin 36):
5V Analog Power Supply. Bypass to AGND
with 10
μ
F tantalum in parallel with 0.1
μ
F ceramic and
connect this pin to Pin 35 with a 10
resistor.
Intermodulaton Distortion
FREQUENCY (kHz)
0
20
A
80
100
0
–20
–40
–60
–80
–100
–120
–140
1604 G06
40
60
160
120 140
f
SAMPLE
= 333kHz
f
IN1
f
IN2
= 32.4kHz
相關PDF資料 |
PDF描述 |
|---|---|
| LTC1604C | Quadruple 2-Input Exclusive-OR Gates 14-SOIC 0 to 70 |
| LTC1604 | High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown(高速，16位，333ksps采樣模數(shù)轉換器（帶關斷）) |
| LTC1605C | 16-Bit, 100ksps, Sampling ADC |
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