參數(shù)資料
型號(hào)： LTC1603
廠商： Linear Technology Corporation
英文描述： High Speed, 16-Bit, 250ksps Sampling A/D Converter with Shutdown
中文描述： 高速，16位，250ksps的采樣與關(guān)機(jī)的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 250K
代理商： LTC1603
1603f
9
LTC1603
APPLICATIO
S I
N
FOR
ATIO
U
W
U
currents are shut down and only leakage current remains
(about 1
μ
A). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47
μ
F
capacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
Figure 2a. Nap Mode to Sleep Mode Timing
t
4
SHDN
CONVST
1603 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
t
2
t
1
CS
CONVST
RD
1603 F03
Figure 3. CS to CONVST Setup Timing
0
C
3500
4000
1603 F04
500
1000
2000
1500
CONVST LOW TIME, t
5
(ns)
2500
3000
4
3
2
1
0
t
CONV
t
ACQ
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset-
ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected. Simi-
larly, if CONVST returns high after the conversion is over
(e.g., CONVST low time >t
CONV
), accuracy is unaffected.
For best results, keep t
5
less than 500ns or greater than
t
CONV
.
Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
t
3
SHDN
CS
1603 F02a
相關(guān)PDF資料
PDF描述
LTC1603CG High Speed, 16-Bit, 250ksps Sampling A/D Converter with Shutdown
LTC1603IG High Speed, 16-Bit, 250ksps Sampling A/D Converter with Shutdown
LTC1604CG Quadruple 2-Input Exclusive-OR Gates 14-PDIP 0 to 70
LTC1604I High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown
LTC1604IG Quadruple 2-Input Exclusive-OR Gates 14-PDIP 0 to 70
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