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參數(shù)資料
| 型號： | LTC1599ACN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 254K |
| 代理商： | LTC1599ACN |
7
LTC1599
PI
FU
CTIO
N
S
U
U
REF (Pin 1):
Reference Input. Typically
±
10V, accepts up
to
±
25V. In 2-quadrant mode, this pin is the reference
input. In 4-quadrant mode, this pin is driven by external
inverting reference amplifier.
R2 (Pin 2):
4-Quadrant Resistor R2. Typically
±
10V,
accepts up to
±
25V. In 2-quadrant operation, connect this
pin to ground. In 4-quadrant mode tie to the REF pin and
to the output of an external amplifier. See Figures 1 and 3.
R
COM
(Pin 3):
Center Tap Point of the Two 4-Quadrant
Resistors R1 and R2. Normally tied to the inverting input
of an external amplifier in 4-quadrant operation, otherwise
connect this pin to ground. See Figures 1 and 3. The ab-
solute maximum voltage range on this pin is –0.3V to 12V.
R1 (Pin 4):
4-Quadrant Resistor R1. Typically
±
10V,
accepts up to
±
25V. In 2-quadrant operation connect this
pin to ground. In 4-quadrant mode tie to R
OFS
(Pin 5). See
Figures 1 and 3.
R
OFS
(Pin 5):
Bipolar Offset Resistor. Typically swings
±
10V, accepts up to
±
25V. In 2-quadrant operation, tie to
R
FB
. In 4-quadrant operation tie to R1.
R
FB
(Pin 6):
Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp. Typically
swings
±
10V. Swings
±
V
REF
.
I
OUT1
(Pin 7):
DAC Current Output. Tie to the inverting
input of the current to voltage converter op amp.
I
OUT2F
(Pin 8):
Force Complement Current Output. Nor-
mally tied to ground.
I
OUT2S
(Pin 9):
Sense Complement Current Output. Nor-
mally tied to ground.
CLVL (Pin 10):
Clear Level. CLVL = 0, selects reset to zero
code. CLVL = 1, selects reset to midscale code. Normally
hardwired to a logic high or a logic low.
LD (Pin 11):
DAC Digital Input Load Control Input. When
LD is taken to a logic low, data is loaded from the input
register into the DAC register, updating the DAC output.
WR (Pin 12): DAC
Digital Write Control Input. When WR
is taken to a logic low, data is loaded from the 8 digital input
pins into the 16-bit wide input register. The MLBYTE pin
determines whether the MSB or LSB byte is loaded.
MLBYTE (Pin 13):
MSB or LSB Byte Select. When MLBYTE
is taken to a logic low and WR is taken to a logic low, data
is loaded from the 8 digital input pins into the first 8 bits
of the 16-bit wide input register. When MLBYTE is taken to
a logic high and WR is taken to a logic low, data is loaded
from the 8 digital input pins into the 8 MSB bits of the input
register.
D7 to D3 (Pins 14 to 18):
Digital Input Data Bits.
DGND (Pin 19):
Digital Ground. Tie to ground.
V
CC
(Pin 20):
The Positive Supply Input. 4.5V
≤
V
CC
≤
5.5V.
Requires a bypass capacitor to ground.
D2 to D0 (Pins 21 to 23):
Digital Input Data Bits.
CLR (Pin 24):
Digital Clear Control Function for the DAC.
When CLR and CLVL are taken to a logic low, the DAC
output and all internal registers are set to zero code. When
CLR is taken to a logic low and CLVL is taken to a logic high,
the DAC output and all internal registers are set to midscale
code.
TRUTH TABLE
Table 1
CONTROL INPUTS
WR
X
CLR
0
1
1
1
1
1
MLBYTE
X
0
1
X
X
X
LD
X
1
1
REGISTER OPERATION
Reset Input and DAC Registers to Zero Scale When CLVL = 0 and Midscale When CLVL = 1
Load the LSB Byte of the Input Register with All 8 Data Bits
Load the MSB Byte of the Input Register with All 8 Data Bits
Load the DAC Register with the Contents of the Input Register
No Register Operation
Flow-Through Mode. The DAC Register and the Selected Input Register Are Transparent. The Unselected Input
Register Retains Its Previous Data Byte. Note Only One Byte Is Transparent at a Time, the Selected Byte Being
Determined By the Logic Value of MLBYTE Prior to WR Being Pulsed Low.
1
1
1
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