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參數(shù)資料
| 型號(hào)： | LTC1598IG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 12BIT SRL 8CH 24SSOP |
| 標(biāo)準(zhǔn)包裝： | 59 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 16.8k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極 |
4
LTC1594/LTC1598
15948fb
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
Analog Input Sample Time
See Figure 1 in Applications Information
1.5
CLK Cycles
fSMPL(MAX)
Maximum Sampling Frequency
See Figure 1 in Applications Information
●
16.8
kHz
tCONV
Conversion Time
See Figure 1 in Applications Information
12
CLK Cycles
tdDO
Delay Time, CLK
↓ to DOUT Data Valid
See Test Circuits
●
250
600
ns
tdis
Delay Time, CS
↑ to DOUT Hi-Z
See Test Circuits
●
135
300
ns
ten
Delay Time, CLK
↓ to DOUT Enabled
See Test Circuits
●
75
200
ns
thDO
Time Output Data Remains Valid After CLK
↓
CLOAD = 100pF
230
ns
tf
DOUT Fall Time
See Test Circuits
●
50
150
ns
tr
DOUT Rise Time
See Test Circuits
●
50
150
ns
tON
Enable Turn-On Time
See Figure 1 in Applications Information
●
260
700
ns
tOFF
Enable Turn-Off Time
See Figure 2 in Applications Information
●
100
300
ns
tOPEN
Break-Before-Make Interval
●
35
160
ns
CIN
Input Capacitance
Analog Inputs On-Channel
20
pF
Off-Channel
5
pF
Digital Input
5
pF
AC CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 5V. Consult factory for 3V
specified devices (LTC1594L/LTC1598L).
Note 4: Increased leakage currents at elevated temperatures cause the S/H
to droop, therefore it is recommended that fCLK ≥ 160kHz at 85°C,
fCLK ≥ 75kHz at 70°C and fCLK ≥ 1kHz at 25°C.
Note 5: VCC = 5V, VREF = 5V and CLK = 320kHz unless otherwise specified.
CSADC and CSMUX pins are tied together during the test.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above VCC. This spec allows 50mV forward
bias of either diode for 4.5V
≤ VCC ≤ 5.5V. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V
input voltage range, it will therefore require a minimum supply voltage of
4.950V over initial tolerance, temperature variations and loading.
Note 8: Recommended operating condition. Not 100% production tested.
Note 9: Channel leakage current is measured after the channel selection.
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY
CURRENT
(
μ
A)
10
100
1000
1
10
100
1594/98 G01
TA = 25°C
VCC = 5V
VREF = 5V
fCLK = 320kHz
Supply Current vs Sample Rate
TEMPERATURE (
°C)
–55
92.0
REFERENCE
CURRENT
(
μ
A)
92.5
93.5
94.0
94.5
–15
25
45
125
1594/98 G03
93.0
–35
5
65
85 105
95.0
VCC = VREF = 5V
fSMPL = 16.8kHz
fCLK = 320kHz
TEMPERATURE (
°C)
–55
200
SUPPLY
CURRENT
(
μ
A)
250
350
400
450
–15
25
45
125
1594/98 G02
300
–35
5
65
85 105
TA = 25°C
VCC = VREF = 5V
fCLK = 320kHz
fSMPL = 16.8kHz
Supply Current vs Temperature
Reference Current vs Temperature
The
● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
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