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參數(shù)資料
| 型號(hào)： | LTC1597C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-Bit and 16-Bit Parallel Low Glitch Multiplying DACs with 4-Quadrant Resistors |
| 中文描述： | 14位和16位并行4低毛刺乘法數(shù)模轉(zhuǎn)換器象限電阻 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 386K |
| 代理商： | LTC1597C |
14
LTC1591/LTC1597
APPLICATIO
S I
FOR
ATIO
U
W
U
U
V
CC
LTC1597
R
FB
R
FB
R
OFS
R
OFS
5V
LD
LD
3
R1
2
R
COM
9
8
28
23
7
22
1
REF
4
5
0.1
μ
F
6
I
OUT1
33pF
V
OUT
=
0V TO
–V
REF
1591/97 F01b
AGND
DGND
WR
10
24 TO 27
WR
CLR
CLR
V
REF
–
+
LT1001
16-BIT DAC
R1
R2
16
DATA
INPUTS
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
–V
REF
(65,535/65,536)
–V
REF
(32,768/65,536) = –V
REF
/2
–V
REF
(1/65,536)
0V
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0000
LSB
ANALOG OUTPUT
VOUT
MSB
1111
1000
0000
0000
Figure 1b. Unipolar Operation (2-Quadrant Multiplication) V
OUT
= 0V to –V
REF
Bipolar Mode
(4-Quadrant Multiplying, V
OUT
= –V
REF
to V
REF
)
The LTC1591/LTC1597 contain on chip all the 4-quadrant
resistors necessary for bipolar operation. 4-quadrant
multiplying operation can be achieved with a minimum of
external components, a capacitor and a dual op amp, as
shown in Figure 2. With a fixed 10V reference, the circuit
shown gives a precision bipolar –10V to 10V output
swing.
Op Amp Selection
Because of the extremely high accuracy of the 14-/16-bit
LTC1591/LTC1597, thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Op amp offset will contribute mostly to output offset and
gain and will have minimal effect on INL and DNL. For the
LTC1597, a 500
μ
V op amp offset will cause about 0.55LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range. The main effects of op amp offset will be
a degradation of zero-scale error equal to the op amp
offset, and a degradation of full-scale error equal to twice
the op amp offset. For the LTC1597, the same 500
μ
V op
amp offset (2mV offset for LTC1591) will cause a 3.3LSB
zero-scale error and a 6.5LSB full-scale error with a 10V
full-scale range.
Op amp input bias current (I
BIAS
) contributes only a zero-
scale error equal to I
BIAS
(R
FB/
R
OFS
) = I
BIAS
(6k). For a
thorough discussion of 16-bit DAC settling time and op
amp selection, refer to Application Note 74, “Component
and Measurement Advances Ensure 16-Bit DAC Settling
Time”
Reference Input and Grounding
For optimum performance the reference input of the
LTC1597 should be driven by a source impedance of less
than 1k
. However, these DACs have been designed to
minimize source impedance effects. An 8k
source im-
pedance degrades both INL and DNL by 0.2LSB.
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding should be used. AGND must be tied to the star
ground with as low a resistance as possible.
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