Conversion Speed with Reduced VREF With reduced reference voltages, the LSB " />
參數(shù)資料
型號(hào)： LTC1594IS#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC A/D CONV 12BIT SRL 4CH 16SOIC
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 16.8k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.6mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極
18
LTC1594/LTC1598
15948fb
Conversion Speed with Reduced VREF
With reduced reference voltages, the LSB step size is
reduced and the LTC1594/LTC1598 internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
VREF are used.
DYNAMIC PERFORMANCE
The LTC1594/LTC1598 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC’s spectral con-
tent can be examined for frequencies outside the funda-
mental. Figure 10 shows a typical LTC1594/LTC1598
plot.
APPLICATIONS INFORMATION
WU
U
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 16.8kHz with a 5V supply, the LTC1594/
LTC1598 maintain above 11 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
FREQUENCY (kHz)
0
–60
–40
0
35
1594/98 G14
–80
–100
12
46
7
–120
–140
–20
MAGNITUDE
(dB)
TA = 25°C
VCC = VREF = 5V
fIN = 5kHz
fCLK = 320kHz
fSMPL = 12.5kHz
Figure 10. LTC1594/LTC1598 Nonaveraged, 4096 Point FFT Plot
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE
NUMBER
OF
BITS
(ENOBs)
8
7
10
9
12
11
10
100
1000
1594/98 G10
6
50
44
62
56
74
68
38
5
4
3
2
1
TA = 25°C
VCC = 5V
fCLK = 320kHz
fSMPL = 16.8kHz
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the fre-
quency band between DC and half of the sampling
frequency. THD is defined as:
THD
=
+++ +
20log
VVV
V
2
3
2
4
2
N
2
1
...
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spec-
tral content with a 16.8kHz sampling rate.
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