APPLICATIONS IN
參數(shù)資料
型號(hào): LTC1594IS#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 7/24頁(yè)
文件大?。?/td> 0K
描述: IC A/D CONV 12BIT SRL 4CH 16SOIC
標(biāo)準(zhǔn)包裝: 50
位數(shù): 12
采樣率(每秒): 16.8k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.6mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極
產(chǎn)品目錄頁(yè)面: 1346 (CN2011-ZH PDF)
15
LTC1594/LTC1598
15948fb
APPLICATIONS INFORMATION
WU
U
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1594/LTC1598 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 10
μFtantalumcapacitorwithleadsasshortaspossible.
If the power supply is clean, the LTC1594/LTC1598 can
also operate with smaller 1
μF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1594/LTC1598 provide a built-in sample-
and-hold (S&H) function to acquire signals through the
selected channel, assuming the ADCIN and MUXOUT
pins are tied together. The S & H of these parts acquire
input signals through the selected channel relative to
COM input during the tSMPL time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1594/LTC1598 allows
conversion of rapidly varying signals. The input voltage
is sampled during the tSMPL time as shown in Figure 7.
The sampling interval begins after tON time once the CS
is pulled low and continues until the second falling CLK
edge after the CS is low (see Figure 7). On this falling CLK
Figure 7. LTC1594/LTC1598 ADCIN and COM Input Settling Windows
CLK
DIN
DOUT
MUXOUT = ADCIN
CH0 TO CH7
SAMPLE
HOLD
“ANALOG” INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
tON
tCONV
CSADC = CSMUX = CS
D2
D1
EN
D0
DON‘T CARE
1ST BIT TEST “COM” INPUT MUST
SETTLE DURING THIS TIME
B11
COM
1594/98 F07
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