IOUT1 (Pin 5): True DAC Current Output. Tied to the" />
參數(shù)資料
型號(hào): LTC1592ACG#TR
廠商: Linear Technology
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 0K
描述: IC D/A CONV 16BIT SOFTSPAN16SSOP
產(chǎn)品培訓(xùn)模塊: LTC275x 18-Bit DAC
標(biāo)準(zhǔn)包裝: 2,000
系列: SoftSpan™
設(shè)置時(shí)間: 2µs
位數(shù): 16
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): *
其它名稱: LTC1592ACGTR
7
LTC1588/LTC1589/LTC1592
1588992fa
IOUT1 (Pin 5): True DAC Current Output. Tied to the
inverting input of the current-to-voltage op amp.
IOUT2 (Pin 6): Complement of DAC Current Output. Nor-
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog
ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground
plane.
VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V.
Requires a 0.1
F bypass capacitor to ground.
SDO (Pin 10): Serial Data Output. Data at this pin is shifted
out on the rising edge of SCK.
SDI (Pin 11): Serial Data Input.
UU
U
PI FU CTIO S
FU CTIO TABLE
U
Table 1
C3
0
1
C2
0
1
0
1
C1
0
1
0
1
0
1
0
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SREG
DATA WORD
Dn IN INPUT
SHIFT REGISTER
Dn
X
Dn
X
BUF1
INPUT
BUFFER
Dn
No Change
DAC
OUTPUT
RANGE
No Change
5V
10V
±5V
±10V
±2.5V
–2.5V to 7.5V
No Change
BUF2
DAC
BUFFER
(DAC OUTPUT)
No Change
Dn
No Change
Copy Data Word Dn in SReg to Buf1
Copy the Data in Buf1 to Buf2
Copy Data Word Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
±5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
±10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
±2.5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
No Operation
Internal Register Status
OPERATION
EACH COMMAND IS EXECUTED
ON THE RISING EDGE OF CS/LD
COMMAND
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
is shifted into the input shift register on rising edge of SCK.
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCK is enabled for shifting data into the input shift register.
When CS/LD is pulled high, SCK is disabled and the control
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to
±15V.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
reference input REF (Pin 15) and the output of the inverting
amplifier tied to RCOM (Pin 1).
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